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LFEC33E-3FN672C 参数 Datasheet PDF下载

LFEC33E-3FN672C图片预览
型号: LFEC33E-3FN672C
PDF下载: 下载PDF文件 查看货源
内容描述: 的LatticeECP / EC系列数据手册 [LatticeECP/EC Family Data Sheet]
分类和应用:
文件页数/大小: 163 页 / 1036 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
 浏览型号LFEC33E-3FN672C的Datasheet PDF文件第56页浏览型号LFEC33E-3FN672C的Datasheet PDF文件第57页浏览型号LFEC33E-3FN672C的Datasheet PDF文件第58页浏览型号LFEC33E-3FN672C的Datasheet PDF文件第59页浏览型号LFEC33E-3FN672C的Datasheet PDF文件第61页浏览型号LFEC33E-3FN672C的Datasheet PDF文件第62页浏览型号LFEC33E-3FN672C的Datasheet PDF文件第63页浏览型号LFEC33E-3FN672C的Datasheet PDF文件第64页  
DC and Switching Characteristics  
LatticeECP/EC Family Data Sheet  
Lattice Semiconductor  
LatticeECP/EC sysCONFIG Port Timing Specifications  
Over Recommended Operating Conditions  
Parameter  
Description  
Min.  
Typ.  
Max.  
Units  
sysCONFIG Byte Data Flow  
t
t
t
t
t
t
t
t
t
Byte D[0:7] Setup Time to CCLK  
7
1
12  
12  
12  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SUCBDI  
HCBDI  
CODO  
SUCS  
HCS  
Byte D[0:7] Hold Time to CCLK  
Clock to Dout in Flowthrough Mode  
CS[0:1] Setup Time to CCLK  
CS[0:1] Hold Time to CCLK  
7
1
Write Signal Setup Time to CCLK  
Write Signal Hold Time to CCLK  
CCLK to BUSY Delay Time  
7
SUWD  
HWD  
1
DCB  
Clock to Out for Read Data  
CORD  
sysCONFIG Byte Slave Clocking  
t
t
t
t
t
t
Byte Slave Clock Minimum High Pulse  
Byte Slave Clock Minimum Low Pulse  
Byte Slave Clock Cycle Time  
6
9
12  
ns  
ns  
ns  
ns  
ns  
ns  
BSCH  
BSCL  
15  
7
BSCYC  
SUSCDI  
HSCDI  
CODO  
Din Setup time to CCLK Slave Mode  
Din Hold Time to CCLK Slave Mode  
Clock to Dout in Flowthrough Mode  
1
sysCONFIG Serial (Bit) Data Flow  
t
t
Din Setup time to CCLK Master Mode  
Din Hold Time to CCLK Master Mode  
7
1
ns  
ns  
SUMCDI  
HMCDI  
sysCONFIG Serial Slave Clocking  
t
t
Serial Slave Clock Minimum High Pulse  
Serial Slave Clock Minimum Low Pulse  
6
6
ns  
ns  
SSCH  
SSCL  
sysCONFIG POR, Initialization and Wake Up  
t
t
t
t
t
t
t
t
Minimum Vcc to INIT High  
25  
50  
2
ms  
us  
ns  
ns  
ms  
ns  
ns  
ns  
ICFG  
Time from tICFG to Valid Master Clock  
Program Pin Pulse Rejection  
VMC  
8
PRGMRJ  
PRGM  
DINIT  
PROGRAMN Low Time to Start Configuration  
INIT Low Time  
1
Delay Time from PROGRAMN Low to INIT Low  
Delay Time from PROGRAMN Low to DONE Low  
User I/O Disable from PROGRAMN Low  
37  
37  
35  
DPPINIT  
DINITD  
IODISS  
User I/O Enabled Time from CCLK Edge During Wake Up  
Sequence  
t
25  
ns  
IOENSS  
t
t
t
Additional Wake Master Clock Signals after Done Pin High  
CFG to INITN Setup Time  
120  
100  
100  
cycles  
ns  
MWC  
SUCFG  
HCFG  
CFG to INITN Hold Time  
ns  
sysCONFIG SPI Port  
t
t
t
t
Init High to CCLK Low  
0
80  
2
ns  
us  
ns  
ns  
CFGX  
Init High to CSSPIN Low  
CCLK Low Before CSSPIN Low  
CCLK Low to Output Valid  
CSSPI  
-
CSCCLK  
SOCDO  
15  
3-24  
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