DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Figure 3-17. Configuration from PROGRAMN Timing
tPRGMRJ
PROGRAMN
tDPPINIT
tDINIT
INITN
tDINITD
DONE
CCLK
tHCFG
tSUCFG
Valid
CFG[2:0]
tIODISS
USER I/O
1. The CFG pins are normally static (hard wired)
Figure 3-18. Wake-Up Timing
PROGRAMN
INITN
Wake-Up
DONE
tMWC
CCLK
tIOENSS
USER I/O
Figure 3-19. sysCONFIG SPI Port Sequence
Capture
CFGx
Capture
OPCODE
Clock 127
Clock 128
t
ICFG
VCC
t
PRGM
PROGRAMN
t
DINITD
DONE
INITN
t
DPPINIT
t
DINIT
t
t
CSPID
CSSPI
t
CSSPIN
CCLK
CFGX
0
1
2
3
4
5
6
7
t
CSCCLK
t
t
SOCDO
SOE
D6
SISPI/BUSY
D7/SPID0
D7
D5 D4 D3 D2 D1 D0
0
Valid Bitstream
XXX
3-28
LATTICE [ LATTICE SEMICONDUCTOR ]
