DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
LatticeECP/EC Family Timing Adders1, 2, 3 (Continued)
Over Recommended Operating Conditions
Buffer Type
HSTL15_II
Description
HSTL_15 class II
-5
-4
-3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.10
0.10
0.08
0.10
-0.05
0.40
-0.05
0.40
0.05
0.25
0.05
0.25
0.01
0.01
0.09
0.07
-0.03
0.36
0.28
0.09
0.07
-0.03
0.36
0.28
0.18
0.10
0.00
0.22
0.14
0.15
0.06
0.01
0.16
0.26
0.04
0.36
0.08
0.36
1.05
0.12
0.12
0.10
0.12
-0.06
0.48
-0.06
0.48
0.07
0.30
0.07
0.30
0.01
0.01
0.11
0.08
-0.04
0.43
0.33
0.11
0.08
-0.04
0.43
0.33
0.21
0.12
0.00
0.26
0.16
0.18
0.08
0.01
0.19
0.31
0.04
0.43
0.10
0.43
1.26
0.14
0.14
0.11
0.14
-0.07
0.56
-0.07
0.56
0.08
0.35
0.08
0.35
0.01
0.01
0.13
0.09
-0.05
0.51
0.39
0.13
0.09
-0.05
0.51
0.39
0.25
0.14
0.00
0.31
0.19
0.21
0.09
0.01
0.22
0.36
0.05
0.50
0.11
0.50
1.46
HSTL15_III
HSTL_15 class III
HSTL15D_I
Differential HSTL 15 class I
Differential HSTL 15 class III
SSTL_3 class I
HSTL15D_III
SSTL33_I
SSTL33_II
SSTL_3 class II
SSTL33D_I
Differential SSTL_3 class I
Differential SSTL_3 class II
SSTL_2 class I
SSTL33D_II
SSTL25_I
SSTL25_II
SSTL_2 class II
SSTL25D_I
Differential SSTL_2 class I
Differential SSTL_2 class II
SSTL_1.8 class I
SSTL25D_II
SSTL18_I
SSTL18D_I
Differential SSTL_1.8 class I
LVTTL 4mA drive
LVTTL33_4mA
LVTTL33_8mA
LVTTL33_12mA
LVTTL33_16mA
LVTTL33_20mA
LVCMOS33_4mA
LVCMOS33_8mA
LVTTL 8mA drive
LVTTL 12mA drive
LVTTL 16mA drive
LVTTL 20mA drive
LVCMOS 3.3 4mA drive
LVCMOS 3.3 8mA drive
LVCMOS33_12mA LVCMOS 3.3 12mA drive
LVCMOS33_16mA LVCMOS 3.3 16mA drive
LVCMOS33_20mA LVCMOS 3.3 20mA drive
LVCMOS25_4mA
LVCMOS25_8mA
LVCMOS 2.5 4mA drive
LVCMOS 2.5 8mA drive
LVCMOS25_12mA LVCMOS 2.5 12mA drive
LVCMOS25_16mA LVCMOS 2.5 16mA drive
LVCMOS25_20mA LVCMOS 2.5 20mA drive
LVCMOS18_4mA
LVCMOS18_8mA
LVCMOS 1.8 4mA drive
LVCMOS 1.8 8mA drive
LVCMOS18_12mA LVCMOS 1.8 12mA drive
LVCMOS18_16mA LVCMOS 1.8 16mA drive
LVCMOS15_4mA
LVCMOS15_8mA
LVCMOS12_2mA
LVCMOS12_6mA
LVCMOS12_4mA
PCI33
LVCMOS 1.5 4mA drive
LVCMOS 1.5 8mA drive
LVCMOS 1.2 2mA drive
LVCMOS 1.2 6mA drive
LVCMOS 1.2 4mA drive
PCI33
1. Timing adders are characterized but not tested on every device.
2. LVCMOS timing measured with the load specified in Switching Test Conditions table of this document.
3. All other standards according to the appropriate specification.
Timing v.G 0.30
3-22
LATTICE [ LATTICE SEMICONDUCTOR ]
