DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Figure 3-14. sysCONFIG Master Serial Port Timing
CCLK (output)
tHMCDI
tSUMCDI
DIN
tCODO
DOUT
Figure 3-15. sysCONFIG Slave Serial Port Timing
tSSCL
tSSCH
CCLK (input)
tHSCDI
tSUSCDI
DIN
tCODO
DOUT
Figure 3-16. Power-On-Reset (POR) Timing
1
V
/V
CC CCAUX
tICFG
INITN
DONE
CCLK 2
tVMC
tHCFG
tSUCFG
CFG[2:0] 3
Valid
1. Time taken from V
or V
, whichever is the last to reach its V
CCAUX
.
MIN
CC
2. Device is in a Master Mode.
3. The CFG pins are normally static (hard wired).
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