DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Parameter
Description
Conditions
Min.
25
Typ.
—
Max.
420
420
210
840
—
Units
MHz
MHz
MHz
MHz
MHz
f
f
f
f
f
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP, CLKOS)
K-Divider Output Frequency (CLKOK)
PLL VCO Frequency
IN
25
—
OUT
OUT2
VCO
PFD
0.195
420
25
—
—
Phase Detector Input Frequency
—
AC Characteristics
Default Duty Cycle
Elected3
t
Output Clock Duty Cycle
Output Phase Accuracy
45
50
55
%
DT
PH
4
t
—
—
—
—
—
—
—
—
250
—
—
—
—
—
0.05
+/- 125
0.02
+/- 200
—
UI
ps
f
f
>= 100MHz
< 100MHz
OUT
1
t
Output Clock Period Jitter
OPJIT
—
UIPP
ps
OUT
t
t
t
t
t
t
t
t
t
Input Clock to Output Clock Skew
Output Clock Pulse Width
PLL Lock-in Time
Divider ratio = integer
At 90% or 10%3
—
SK
1
ns
W
2
—
150
µs
LOCK
PA
Programmable Delay Unit
Input Clock Period Jitter
External Feedback Delay
Input Clock High Time
Input Clock Low Time
RST Pulse Width
100
—
450
ps
+/- 200
10
ps
IPJIT
—
ns
FBKDLY
HI
90% to 90%
10% to 10%
0.5
0.5
10
—
ns
—
ns
LO
—
ns
RST
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock.
2. Output clock is valid after t
for PLL reset and dynamic delay adjustment.
LOCK
3. Using LVDS output buffers.
4. Relative to CLKOP.
Timing v.G 0.30
3-23
LATTICE [ LATTICE SEMICONDUCTOR ]
