Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
Boundary Scan Waveforms and Timing Specifications
Symbol
Parameter
Min.
40
20
20
8
Max.
—
Units
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
TCK [BSCAN test] clock cycle
BTCP
TCK [BSCAN test] pulse width high
—
ns
BTCH
BTCL
TCK [BSCAN test] pulse width low
—
ns
TCK [BSCAN test] setup time
—
ns
BTSU
BTH
TCK [BSCAN test] hold time
10
50
—
—
—
8
—
ns
TCK [BSCAN test] rise and fall time
—
mV/ns
ns
BRF
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to data output disable
TAP controller falling edge of clock to data output enable
BSCAN test Capture register setup time
10
10
10
—
BTCO
BTOZ
ns
ns
BTVO
BTCPSU
BTCPH
BTUCO
BTUOZ
BTUOV
ns
BSCAN test Capture register hold time
10
—
—
—
—
ns
BSCAN test Update reg, falling edge of clock to valid output
BSCAN test Update reg, falling edge of clock to output disable
BSCAN test Update reg, falling edge of clock to output enable
25
25
25
ns
ns
ns
39
LATTICE [ LATTICE SEMICONDUCTOR ]
