Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000Z Timing Adders (Cont.)1
-45
-5
-75
Adder
Type
Base
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
Optional Delay Adders
t
t
t
t
Input register delay
—
—
1.30
0.45
—
—
1.30
0.45
—
—
1.30
0.50
ns
ns
INDIO
EXP
INREG
MCELL
Product term expander
delay
t
—
Output routing pool
delay
ORP
BLA
—
—
0.40
0.05
—
—
0.40
0.05
—
—
0.40
0.05
ns
ns
t
t
Additional block load-
ing adder
ROUTE
t
Input Adjusters
IOI
LVTTL_in
t
t
t
t
Using LVTTL standard
—
—
0.60
0.60
—
—
0.60
0.60
—
—
0.60
0.60
ns
ns
IN, GCLK_IN, GOE
LVCMOS33_in
t
t
Using LVCMOS 3.3
standard
IN, GCLK_IN, GOE
LVCMOS25_in
LVCMOS18_in
PCI_in
t
t
t
t
t
Using LVCMOS 2.5
standard
IN, GCLK_IN, GOE
—
—
—
0.60
0.00
0.60
—
—
—
0.60
0.00
0.60
—
—
—
0.60
0.00
0.60
ns
ns
ns
t
t
Using LVCMOS 1.8
standard
IN, GCLK_IN, GOE
t
t
Using PCI compatible
input
IN, GCLK_IN, GOE
t
Output Adjusters
IOO
LVTTL_out
t
t
t
t
t
t
t
t
Output configured as
TTL buffer
BUF, EN, DIS
—
—
—
—
—
—
0.20
0.20
0.10
0.00
0.20
1.00
—
—
—
—
—
—
0.20
0.20
0.10
0.00
0.20
1.00
—
—
—
—
—
—
0.20
0.20
0.10
0.00
0.20
1.00
ns
ns
ns
ns
ns
LVCMOS33_out
LVCMOS25_out
LVCMOS18_out
PCI_out
t
t
Output configured as
3.3V buffer
BUF, EN, DIS
t
t
Output configured as
2.5V buffer
BUF, EN, DIS
t
t
Output configured as
1.8V buffer
BUF, EN, DIS
t
t
Output configured as
PCI compatible buffer
BUF, EN, DIS
Slow Slew
t
Output configured for
slow slew rate
BUF, EN
ns
Note: Open drain timing is the same as corresponding LVCMOS timing.
Timing v.2.2
1. Refer to Technical Note TN 1004, ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these
adders.
38
LATTICE [ LATTICE SEMICONDUCTOR ]
