Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000V/B/C Timing Adders1
-25
-27
-3
-35
Adder
Type
Base
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
Optional Delay Adders
t
t
t
t
t
Input register delay
—
—
—
—
0.95
0.33
0.05
0.03
—
—
—
—
1.00
0.33
—
—
—
—
1.00
0.33
—
—
—
—
1.00
0.33
ns
ns
INDIO
INREG
Product term expander
delay
t
EXP
MCELL
—
Output routing pool delay
0.05
0.05
0.05
0.05
0.05
0.05
ns
ns
ORP
BLA
Additional block loading
adder
t
ROUTE
t
Input Adjusters
IOI
t , t
t
,
,
,
,
,
IN GCLK_IN
GOE
LVTTL_in
Using LVTTL standard
—
—
—
—
—
0.60
0.60
0.60
0.00
0.60
—
—
—
—
—
0.60
0.60
0.60
0.00
0.60
—
—
—
—
—
0.60
0.60
0.60
0.00
0.60
—
—
—
—
—
0.60
0.60
0.60
0.00
0.60
ns
ns
ns
ns
ns
t , t
Using LVCMOS 3.3
standard
IN GCLK_IN
GOE
LVCMOS33_in
LVCMOS25_in
LVCMOS18_in
PCI_in
t
t , t
Using LVCMOS 2.5
standard
IN GCLK_IN
GOE
t
t , t
Using LVCMOS 1.8
standard
IN GCLK_IN
GOE
t
t , t
Using PCI compatible
input
IN GCLK_IN
GOE
t
t
Output Adjusters
IOO
Output configured as
TTL buffer
LVTTL_out
t
, t , t
—
—
—
—
—
—
0.20
0.20
0.10
0.00
0.20
1.00
—
—
—
—
—
—
0.20
0.20
0.10
0.00
0.20
1.00
—
—
—
—
—
—
0.20
0.20
0.10
0.00
0.20
1.00
—
—
—
—
—
—
0.20
0.20
0.10
0.00
0.20
1.00
ns
ns
ns
ns
ns
ns
BUF EN DIS
Output configured as
3.3V buffer
LVCMOS33_out t
LVCMOS25_out t
LVCMOS18_out t
, t , t
BUF EN DIS
Output configured as
2.5V buffer
, t , t
BUF EN DIS
Output configured as
1.8V buffer
, t , t
BUF EN DIS
Output configured as
PCI compatible buffer
PCI_out
t
, t , t
BUF EN DIS
Output configured for
slow slew rate
Slow Slew
t
, t
BUF EN
Note: Open drain timing is the same as corresponding LVCMOS timing.
Timing v.3.2
1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.
35
LATTICE [ LATTICE SEMICONDUCTOR ]
