Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000V/B/C/Z Power Supply and NC Connections1
Signal
44-pin TQFP2
48-pin TQFP2
56-ball csBGA3
100-pin TQFP2
128-pin TQFP2
VCC
11, 33
12, 36
K2, A9
25, 40, 75, 90
32, 51, 96, 115
VCCO0
VCCO (Bank 0)
6
6
F3
E8
13, 33, 95
45, 63, 83
3, 17, 30, 41, 122
58, 67, 81, 94, 105
VCCO1
VCCO (Bank 1)
28
30
GND
12, 34
5
13, 37
5
H3, C8
D3
1, 26, 51, 76
7, 18, 32, 96
46, 57, 68, 82
1, 33, 65, 97
GND (Bank 0)
GND (Bank 1)
NC
10, 24, 40, 113, 123
49, 59, 74, 88, 104
27
29
G8
4032Z: A8, B10, E1,
E3, F8, F10, J1, K3
—
—
—
—
1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with
the bank shown.
2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.
3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order
ascending horizontally.
43
LATTICE [ LATTICE SEMICONDUCTOR ]
