Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000V/B/C Timing Adders1 (Cont.)
-5
-75
-10
Adder
Type
Base
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
Optional Delay Adders
t
t
t
t
t
t
Input register delay
—
—
—
—
1.00
0.33
0.05
0.05
—
—
—
—
1.00
0.33
0.05
0.05
—
—
—
—
1.00
0.33
0.05
0.05
ns
ns
ns
ns
INDIO
EXP
INREG
MCELL
Product term expander delay
Output routing pool delay
—
ORP
BLA
t
Additional block loading adder
ROUTE
t
Input Adjusters
IOI
t , t
t
,
,
,
,
,
IN GCLK_IN
GOE
LVTTL_in
Using LVTTL standard
—
—
—
—
—
0.60
0.60
0.60
0.00
0.60
—
—
—
—
—
0.60
0.60
0.60
0.00
0.60
—
—
—
—
—
0.60
0.60
0.60
0.00
0.60
ns
ns
ns
ns
ns
t , t
IN GCLK_IN
GOE
LVCMOS33_in
LVCMOS25_in
LVCMOS18_in
PCI_in
Using LVCMOS 3.3 standard
Using LVCMOS 2.5 standard
Using LVCMOS 1.8 standard
Using PCI compatible input
t
t , t
IN GCLK_IN
GOE
t
t , t
IN GCLK_IN
GOE
t
t , t
IN GCLK_IN
GOE
t
t
Output Adjusters
IOO
LVTTL_out
t
, t , t
Output configured as TTL buffer
Output configured as 3.3V buffer
Output configured as 2.5V buffer
Output configured as 1.8V buffer
—
—
—
—
0.20
0.20
0.10
0.00
—
—
—
—
0.20
0.20
0.10
0.00
—
—
—
—
0.20
0.20
0.10
0.00
ns
ns
ns
ns
BUF EN DIS
LVCMOS33_out t
LVCMOS25_out t
LVCMOS18_out t
, t , t
BUF EN DIS
, t , t
BUF EN DIS
, t , t
BUF EN DIS
Output configured as PCI compatible
buffer
PCI_out
t
, t , t
—
—
0.20
1.00
—
—
0.20
1.00
—
—
0.20
ns
BUF EN DIS
Slow Slew
t
, t
Output configured for slow slew rate
1.00
ns
BUF EN
Note: Open drain timing is the same as corresponding LVCMOS timing.
Timing v.3.2
1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.
36
LATTICE [ LATTICE SEMICONDUCTOR ]
