Specifications ispLSI 2128VE
External Timing Parameters
Over Recommended Operating Conditions
TEST3
COND.
-135
-100
PARAMETER
#
DESCRIPTION1
UNITS
MIN. MAX. MIN. MAX.
—
—
7.5
10.0
—
—
—
10.0
13.0
—
A
1
2
3
4
5
6
7
8
9
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback2
ns
ns
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd1
A
pd2
135
100
143
5.0
—
100
77
A
MHz
MHz
MHz
ns
max
1
—
—
—
—
—
A
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
(
)
max (Ext.)
max (Tog.)
su1
tsu2 + tco1
—
100
6.5
—
—
—
—
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
4.0
—
5.0
—
ns
co1
0.0
6.0
—
0.0
8.0
—
—
—
A
ns
h1
—
—
ns
su2
5.0
—
6.0
—
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay, ORP Bypass
13 Ext. Reset Pulse Duration
ns
co2
0.0
—
0.0
—
—
A
ns
h2
9.0
—
12.5
—
ns
r1
5.0
—
6.5
—
—
B
ns
rw1
12.0
12.0
7.0
7.0
—
15.0
15.0
9.0
9.0
—
14 Input to Output Enable
ns
ptoeen
ptoedis
goeen
goedis
wh
—
—
C
15 Input to Output Disable
ns
—
—
B
16 Global OE Output Enable
ns
—
—
C
17 Global OE Output Disable
ns
3.5
3.5
5.0
5.0
—
—
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
ns
—
—
ns
wl
Table 2-0030B/2128VE
v.1.0
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
6
LATTICE [ LATTICE SEMICONDUCTOR ]
