Specifications ispLSI 2128VE
ispLSI 2128VE Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Comb 4 PT Bypass #23
Ded. In
#21
I/O Delay
#20
GRP
#22
Reg 4 PT Bypass
GLB Reg Bypass
#28
ORP Bypass
#37
#38,
39
I/O Pin
(Output)
I/O Pin
(Input)
#24
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
D
Q
#36
#25, 26, 27
RST
#45
#29, 30,
31, 32
Reset
Control
PTs
RE
OE
CK
#33, 34,
35
#40, 41
#43, 44
#42
Y0,1,2
GOE 0
0491/2032
Derivations of
t
su,
= Logic + Reg su - Clock (min)
= ( io + grp + 20ptxor) + ( gsu) - (
= (#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
th and tco from the Product Term Clock
t
su
t
t
t
t
tio + tgrp + tptck(min))
2.8ns = (0.5 + 0.2 + 2.8) + (0.8) - (0.5 + 0.2 + 0.8)
t
h
= Clock (max) + Reg h - Logic
= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
= (#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
2.5ns
co
= (0.5 + 0.2 + 3.6) + (1.7) - (0.5 + 0.2 + 2.8)
t
= Clock (max) + Reg co + Output
= (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
= (#20 + #22 + #35) + (#31) + (#36 + #38)
= (0.5 + 0.2 + 3.6) + (0.2) + (1.1 + 1.4)
7.0ns
Note: Calculations are based upon timing specifications for the ispLSI 2128VE-250L.
Table 2-0042/2128VE
v.1.0
9
LATTICE [ LATTICE SEMICONDUCTOR ]
