Specifications ispLSI 2128VE
Functional Block Diagram
Figure 1. ispLSI 2128VE Functional Block Diagram (128-I/O and 64-I/O Versions)
RESET
RESET
Input Bus
Input Bus
GOE 0
GOE 1
GOE 0
GOE 1
Output Routing Pool (ORP)
D6
D5
Output Routing Pool (ORP)
D2
D1
Output Routing Pool (ORP)
Megablock
Generic Logic
Megablock
Generic Logic
IN 5
IN 4
IN 5*
IN 4*
D7
D4
D0
D3
D7
D6
D5
D2
D1
D0
D4
D3
Blocks (GLBs)
Blocks (GLBs)
I/O 95
I/O 94
I/O 93
I/O 92
I/O 47
I/O 46
I/O 45
I/O 44
C7
C6
C7
C6
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
A0
A0
I/O 91
I/O 90
I/O 89
I/O 88
I/O 4
I/O 5
I/O 6
I/O 7
I/O 87
I/O 86
I/O 85
I/O 84
A1
I/O 43
I/O 42
I/O 41
I/O 40
A1
C5
C4
C5
C4
I/O 8
I/O 9
I/O 10
I/O 11
I/O 4
I/O 5
I/O 6
I/O 7
I/O 83
I/O 82
I/O 81
I/O 80
A2
A3
A2
A3
Global
Routing
Pool
Global
Routing
Pool
I/O 12
I/O 13
I/O 14
I/O 15
I/O 79
I/O 78
I/O 77
I/O 76
C3
C2
C3
C2
(GRP)
(GRP)
I/O 16
I/O 17
I/O 18
I/O 19
I/O 75
I/O 74
I/O 73
I/O 72
I/O 39
I/O 38
I/O 37
I/O 36
A4
A5
A4
A5
I/O 8
I/O 9
I/O 10
I/O 11
I/O 20
I/O 21
I/O 22
I/O 23
I/O 71
I/O 70
I/O 69
I/O 68
C1
C0
C1
C0
I/O 24
I/O 25
I/O 26
I/O 27
I/O 67
I/O 66
I/O 65
I/O 64
I/O 35
I/O 34
I/O 33
I/O 32
A6
A7
A6
A7
I/O 12
I/O 13
I/O 14
I/O 15
I/O 28
I/O 29
I/O 30
I/O 31
TDI/IN 0
TMS/IN 1
TDI/IN 0
TMS/IN 1
B0
B1
B2
B3
B5
B6
B7
B4
B0
B1
B2
B3
B5
B6
B7
B4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
BSCAN
BSCAN
0139B/2128VE
0139B/2128VE.64IO
*Not available on 84-PLCC Device
The 128-I/O 2128VE contains 128 I/O cells, while the 64- Y1, Y2) or an asynchronous clock can be selected on a
I/O version contains 64 I/O cells. Each I/O cell is directly GLB basis. The asynchronous or Product Term clock
connected to an I/O pin and can be individually pro- can be generated in any GLB for its own clock.
grammed to be a combinatorial input, output or
Programmable Open-Drain Outputs
bi-directional I/O pin with 3-state control. The signal
levelsareTTLcompatiblevoltagesandtheoutputdrivers
In addition to the standard output configuration, the
can source 4mA or sink 8mA. Each output can be
outputs of the ispLSI 2128VE are individually program-
programmed independently for fast or slow output slew
mable, either as a standard totem-pole output or an
rate to minimize overall output switching noise. Device
open-drain output. The totem-pole output drives the
pins can be safely driven to 5V signal levels to support
specified Voh and Vol levels, whereas the open-drain
mixed-voltage systems.
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
pull-up. This output configuration is controlled by a pro-
two or one ORPs are connected together to make a
grammable fuse. The default configuration when the
Megablock (see Figure 1). The outputs of the eight GLBs
device is in bulk erased state is totem-pole configuration.
are connected to a set of 32 or 16 universal I/O cells by
The open-drain/totem-pole option is selectable through
the two or one ORPs. Each ispLSI 2128VE device
the Lattice software tools.
contains four Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs andallof theinputs fromthebi-directionalI/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2128VE device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
2
LATTICE [ LATTICE SEMICONDUCTOR ]
