Specifications ispLSI 2128VE
External Timing Parameters
Over Recommended Operating Conditions
TEST3
COND.
-250
-180
PARAMETER
#
DESCRIPTION1
UNITS
MIN. MAX. MIN. MAX.
A
A
A
–
1
2
3
4
5
6
7
8
9
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback2
–
–
4.0
6.0
–
–
–
5.0
7.5
–
ns
ns
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd1
pd2
250
158
277
2.5
–
180
125
200
3.5
–
MHz
MHz
MHz
ns
max
1
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
(
)
–
–
max (Ext.)
max (Tog.)
su1
tsu2 + tco1
–
–
–
–
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
–
–
A
–
3.0
–
3.5
–
ns
co1
0.0
3.3
–
0.0
4.5
–
ns
h1
–
–
–
ns
su2
A
–
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay, ORP Bypass
13 Ext. Reset Pulse Duration
3.7
–
4.5
–
ns
co2
0.0
–
0.0
–
ns
h2
A
–
6.0
–
7.0
–
ns
r1
3.5
–
4.0
–
ns
rw1
B
C
B
C
–
14 Input to Output Enable
6.0
6.0
4.0
4.0
–
10.0
10.0
5.0
5.0
–
ns
ptoeen
ptoedis
goeen
goedis
wh
15 Input to Output Disable
–
–
ns
16 Global OE Output Enable
–
–
ns
17 Global OE Output Disable
–
–
ns
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
1.8
1.8
2.5
2.5
ns
–
–
–
ns
wl
Table 2-0030A/2128VE
v.1.0
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
5
LATTICE [ LATTICE SEMICONDUCTOR ]
