Specifications ispLSI 2128VE
Internal Timing Parameters1
Over Recommended Operating Conditions
-250
-180
2
PARAMETER
Inputs
#
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX.
20 Input Buffer Delay
—
—
0.5
0.7
—
—
0.5
1.1
ns
ns
t
io
21 Dedicated Input Delay
tdin
GRP
grp
GLB
22 GRP Delay
—
0.2
—
0.6
ns
t
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
25 1 Product Term/XOR Path Delay
—
—
—
—
—
—
0.8
1.7
—
—
—
—
1.5
2.0
2.8
2.8
2.8
0.0
—
—
—
—
—
—
—
1.2
2.3
—
—
—
—
1.9
2.4
3.4
3.4
3.4
0.0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
4ptbpc
4ptbpr
1ptxor
20ptxor
xoradj
gbp
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay3
28 GLB Register Bypass Delay
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
gsu
—
—
gh
0.2
0.3
3.7
2.9
0.3
0.6
4.3
5.9
gco
gro
ptre
ptoe
ptck
0.8 3.6
1.0 4.0
ORP
36 ORP Delay
—
—
1.1
0.4
—
—
1.4
0.4
ns
ns
t
orp
37 ORP Bypass Delay
torpbp
Outputs
38 Output Buffer Delay
—
—
—
—
—
1.4
2.0
2.4
2.4
1.6
—
—
—
—
—
1.6
2.0
3.0
3.0
2.0
ns
ns
ns
ns
ns
t
t
t
t
t
ob
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
sl
oen
odis
goe
Clocks
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
1.0 1.0
1.2 1.2
1.2 1.2
1.4 1.4
ns
ns
t
gy0
tgy1/2
Global Reset
gr
45 Global Reset to GLB
—
3.9
—
4.4
ns
t
Table 2-0036A/2128VE
v.1.0
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
LATTICE [ LATTICE SEMICONDUCTOR ]
