iCE40 HX-Series Ultra-Low Power Family
Programmable Input/Output (PIO) Block
Table 9 provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths
shown in Figure 7 and Figure 8. The timing shown is for the LVCMOS25 I/O standard in all I/O banks. The
iCEcube2 development software reports timing adjustments for other I/O standards.
Figure 7: Programmable I/O (PIO) Pad-to-Pad Timing Circuit
PAD
PAD
PIO
PIO
Figure 8: Programmable I/O (PIO) Sequential Timing Circuit
PAD
PAD
PIO
PIO
INFF
OUTFF
D
Q
D
Q
GBIN
GBUF
Table 9: Typical Programmable Input/Output (PIO) Timing (LVCMOS25)
Nominal VCC
1.2 V
Description
units
Typ.
Synchronous Output Paths
OUTFF
Delay from clock input on OUTFF output flip-flop to PIO output
pad.
tOCKO
PIO
output
3.1
1.4
ns
clock
input
GBIN
input
OUTFF
clock
input
Global Buffer Input (GBIN) delay, though Global Buffer (GBUF)
clock network to clock input on the PIO OUTFF output flip-flop.
tGBCKIO
ns
Synchronous Input Paths
Setup time on PIO input pin to INFF input flip-flop before active
clock edge on GBIN input, including interconnect delay.
tSUPDIN
PIO
GBIN
input
PIO
0
ns
ns
input
GBIN
input
Hold time on PIO input to INFF input flip-flop after active clock
edge on the GBIN input, including interconnect delay.
tHDPDIN
1.6
input
Pad to Pad
Inter-
Asynchronous delay from PIO input pad to adjacent
tPADIN
PIO
input
Inter-
1.8
3.4
ns
ns
connect interconnect.
Asynchronous delay from adjacent interconnect to PIO output
pad including interconnect delay.
tPADO
PIO
output
connect
Lattice Semiconductor Corporation
(1.32, 03-OCT-2012)
www.latticesemi.com/
7
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