DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
SERDES External Reference Clock (LatticeECP2M Family Only)
The external reference clock selection and its interface are a critical part of system applications for this product.
Table 3-13 specifies reference clock requirements, over the full range of operating conditions.
Table 3-13. External Reference Clock Specification (refclkp/refclkn)
Symbol
Description
Frequency range
Min.
25
Typ.
—
Max.
320
Units
MHz
ppm
mV, p-p
V
F
F
REF
REF-PPM
Frequency tolerance
Input swing, single-ended clock1
-300
100
0
—
300
V
V
V
V
—
1200
REF-IN-SE
REF-IN
Input levels
—
V
+ 0.8
CCP
Input common mode range (DC coupled)
Input common mode range (AC coupled)2
Duty cycle3
0.5
0
—
1.2
1.5
V
REF-CM-DC
REF-CM-AC
—
V
D
40
—
60
%
REF
T
T
Z
Rise time (20% to 80%)
Fall time (80% to 20%)
Input termination
500
500
50/2K
—
1000
1000
ps
REF-R
ps
REF-F
Ohms
pF
REF-IN-TERM
C
Input capacitance4
—
1.5
REF-IN-CAP
1. The signal swing for a single-ended input clock must be as large as the p-p differential swing of a differential input clock to get the same
gain at the input receiver. Lower swings for the clock may be possible, but will tend to increase jitter.
2. When AC coupled, the input common mode range is determined by:
(Min input level) + (Peak-to-peak input swing)/2 ≤ (Input common mode voltage) ≤ (Max input level) - (Peak-to-peak input swing)/2
3. Measured at 50% amplitude.
4. Input capacitance of 1.5pF is total capacitance, including both device and package.
Figure 3-13. Jitter Transfer
5.00
0.00
Jitter T.
Gain@25°C,1.20V,
PJ=100ps
-5.00
-10.00
-15.00
-20.00
-25.00
0.1
1
10
100
Frequency (MHz)
Note: This graph is for a nominal device.
SERDES Power-Down/Power-Up Specification
Table 3-14. Power-Down and Power-Up Specification
Symbol
Description
Max.
10
Units
s
t
t
Power-down time after all power down register bitsset to ‘0’
Power-up time after all power down register bits set to ‘1’
PWRDN
PWRUP
5
ms
3-41
LATTICE [ LATTICE SEMICONDUCTOR ]
