DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Table 3-9. SERDES/PCS Latency Breakdown (Parallel Clock Cycle)
Item
Description
Min.
Average
Max.
Bypass
Transmit Data Latency
T1
T2
T3
T4
FPGA Bridge Transmit2
1
2
2
3
2
2
5
2
1
1
1
8b10b Encoder
SERDES Bridge Transmit
Serializer3
2
2.4
Receive Data Latency
R1
R2
R3
R4
R5
R6
Deserializer3
1.2
2
SERDES Bridge Receive
Word Alignment
2
4
1
7
1
2
4
1
0
1
1
1
4
8b10b Decoder
1
1
Clock Tolerance Compensation
FPGA Bridge Receive2
15
3
23
5
1. PCS internal Parallel Clock. This clock rate is same as the rxfullclk in table 8-6.
2. FPGA Bridge latency varies by UP/DOWN Sample FIFO read/write. These numbers were presented for
8bit/10bit interface. The depth of Down Sample/Up Sample FIFO is 4. The earliest read can be done after
write clock cycle (1 clock) in Down Sample FIFO. The latest read will be done after the FIFO is full (4 + 1
= 5). For 16b/20b interface, the numbers become doubled. Min = 2, Max = 10. This latency depends on
the internal FIFO flag operation.
3. The maximum latency applies to bit0.
Bit1 latency = Bit0 latency + 1 UI.
Bit2 latency = Bit0 latency + 2 UI.
Figure 3-12.Transmitter and Receiver Block Diagram
SERDES
SERDES Bridge
Recovered Clock
FPGA Core
PCS
FPGA Bridge
REFCLK
FPGA
EBRD Clock
R4
R5
R3
R6
R1
R2
WA
DEC
Elastic
Buffer
FIFO
HDINPi
HDINNi
Down
Sample
FIFO
Receive Data
Deserializer
1:8/1:10
Polarity
Adjust
EQ
CDR
BYPASS
BYPASS
BYPASS
Receiver
REFCLK
BYPASS
FPGA
Receive Clock
Transmit Clock
TX PLL
T2
T1
T3
T4
Encoder
Up
Sample
FIFO
Polarity
Adjust
Transmit Data
HDOUTPi
HDOUTNi
Serializer
8:1/10:1
BYPASS
BYPASS
BYPASS
Transmitter
FPGA
Transmit Clock
3-39
LATTICE [ LATTICE SEMICONDUCTOR ]
