DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
SERDES High Speed Data Receiver (LatticeECP2M Family Only)
Table 3-10. Serial Input Data Specifications
Symbol
Description
Min.
Typ.
Max.
Units
Stream of nontransitions1
7 @ 3.125 Gbps
20 @ 1.25 Gbps
RX-CID
Bits
(CID = Consecutive Identical Digits) @ 10-12 BER
Differential input sensitivity
S
V
V
V
V
T
100
0
—
—
—
—
—
50
9
—
mV, p-p
V
RX-DIFF-S
Input levels
V
+ 0.8
RX-IN
CCRX
Input common mode range (DC coupled)
Input common mode range (AC coupled)3
CDR re-lock time2
0.5
0
1.2
1.5
V
RX-CM-DC
RX-CM-AC
V
—
—
—
3000
Bits
Ohms
dB
RX-RELOCK
RX-TERM
Z
Input termination 50/75 Ohm/High Z
Return loss (without package)
RL
—
RX-RL
1. This is the number of bits allowed without a transition on the incoming data stream when using DC coupling.
2. This is the typical number of bit times to re-lock to a new phase or frequency within +/- 300 ppm, assuming 8b10b encoded data.
3. AC coupling is used to interface to LVPECL and LVDS.
Input Data Jitter Tolerance
A receiver’s ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface stan-
dards have recognized the dependency on jitter type and have recently modified specifications to indicate toler-
ance levels for different jitter types as they relate to specific protocols (e.g. FC, etc.). Sinusoidal jitter is considered
to be a worst case jitter type.
Table 3-11. Receiver Total Jitter Tolerance Specification1
Description
Deterministic
Random
Total
Frequency
Condition
Min.
—
—
—
—
—
—
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
Max.
0.54
0.26
0.80
0.61
0.22
0.81
0.53
0.22
0.80
0.42
0.10
0.60
Units
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
600 mV differential eye
3.125 Gbps 600 mV differential eye
600 mV differential eye
Deterministic
Random
Total
600 mV differential eye
2.5 Gbps
600 mV differential eye
600 mV differential eye
600 mV differential eye
Deterministic
Random
Total
1.25 Gbps 600 mV differential eye
600 mV differential eye
Deterministic
Random
Total
600 mV differential eye
250 Mbps2 600 mV differential eye
600 mV differential eye
1. Values are measured with PRBS 27-1, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, voltages are nominal,
room temperature.
2. Jitter specification is limited by measurement equipment capability.
Table 3-12. Periodic Receiver Jitter Tolerance Specification1
Description
Frequency
3.125 Gbps 600 mV differential eye
2.5 Gbps 600 mV differential eye
Condition
Min.
—
Typ.
—
Max.
0.20
0.22
0.20
0.08
Units
UI, p-p
UI, p-p
UI, p-p
UI, p-p
—
—
Periodic
1.25 Gbps 600 mV differential eye
250 Mbps2 600 mV differential eye
—
—
—
—
1. Values are measured with PRBS 27-1, all channels operating.
2. Jitter specification is limited by measurement equipment capability.
3-40
LATTICE [ LATTICE SEMICONDUCTOR ]
