DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2/M sysCONFIG Port Timing Specifications
Over Recommended Operating Conditions
Parameter
Description
Min.
Max.
Units
sysCONFIG Byte Data Flow
t
t
t
t
t
t
t
t
t
Byte D[0:7] Setup Time to CCLK
7
1
—
—
12
—
—
—
—
12
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
SUCBDI
HCBDI
CODO
SUCS
HCS
Byte D[0:7] Hold Time to CCLK
CCLK to DOUT in Flowthrough Mode
CSN[0:1] Setup Time to CCLK
CSN[0:1] Hold Time to CCLK
Write Signal Setup Time to CCLK
Write Signal Hold Time to CCLK
CCLK to BUSY Delay Time
—
7
1
7
SUWD
HWD
1
—
—
DCB
CCLK to Out for Read Data
CORD
sysCONFIG Byte Slave Clocking
t
t
t
Byte Slave CCLK Minimum High Pulse
Byte Slave CCLK Minimum Low Pulse
Byte Slave CCLK Cycle Time
6
9
—
—
—
ns
ns
ns
BSCH
BSCL
15
BSCYC
sysCONFIG Serial (Bit) Data Flow
t
t
t
DI Setup Time to CCLK Slave Mode
DI Hold Time to CCLK Slave Mode
CCLK to DOUT in Flowthrough Mode
7
1
—
—
12
ns
ns
ns
SUSCDI
HSCDI
CODO
—
sysCONFIG Serial Slave Clocking
t
t
Serial Slave CCLK Minimum High Pulse
Serial Slave CCLK Minimum Low Pulse
6
6
—
—
ns
ns
SSCH
SSCL
sysCONFIG POR, Initialization and Wake-up
t
t
t
t
t
t
t
t
t
t
Minimum Vcc to INITN High
Time from t to Valid Master CCLK
—
—
—
25
—
—
—
—
—
120
28
2
ms
us
ICFG
VMC
ICFG
PROGRAMN Pin Pulse Rejection
8
ns
PRGMRJ
PRGM
PROGRAMN Low Time to Start Configuration
PROGRAMN High to INITN High Delay
—
1
ns
ms
ns
DINIT
Delay Time from PROGRAMN Low to INITN Low
Delay Time from PROGRAMN Low to DONE Low
User I/O Disable from PROGRAMN Low
37
37
35
25
—
DPPINIT
DPPDONE
IODISS
IOENSS
MWC
ns
ns
User I/O Enabled Time from CCLK Edge During Wake-up Sequence
Additional Wake Master Clock Signals after DONE Pin High
ns
cycles
sysCONFIG SPI Port
t
t
t
t
t
t
INITN High to CCLK Low
—
1
µs
us
ns
ns
ns
ns
CFGX
INITN High to CSSPIN Low
—
2
CSSPI
CSCCLK
SOCDO
SOE
CCLK Low before CSSPIN Low
CCLK Low to Output Valid
0
—
—
15
CSSPIN[0:1] Active Setup Time
CSSPIN[0:1] Low to First CCLK Edge Setup Time
300
—
300+3cyc
600+6cyc
CSPID
Max. CCLK Frequency - SPI Flash Read Opcode (0x03)
(SPIFASTN = 1)
—
—
20
50
MHz
MHz
f
MAXSPI
Max. CCLK Frequency - SPI Flash Fast Read Opcode (0x0B)
(SPIFASTN = 0)
3-44
LATTICE [ LATTICE SEMICONDUCTOR ]
