DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
SERDES High Speed Data Transmitter(LatticeECP2M Family Only)1, 2
Table 3-7. Serial Output Timing and Levels
Symbol
Description
Frequency
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
—
Min.
—
Typ.
1.25
1.4
1.0
1.2
0.8
70
Max.
—
Units
V, p-p
V, p-p
V, p-p
V, p-p
V
V
V
V
V
V
Differential swing (1.25V setting)1, 2
Differential swing (1.4V setting)1, 2
Differential swing (1.0V setting)1, 2
Differential swing (1.2V setting)1, 2
Output common mode voltage
Rise time (20% to 80%)
TX-DIFF-P-P-1.25
TX-DIFF-P-P-1.4
TX-DIFF-P-P-1.0
TX-DIFF-P-P-1.2
OCM
—
—
—
—
—
—
—
—
T
T
—
—
—
ps
TX-R
Fall time (80% to 20%)
—
—
70
—
ps
TX-F
Output Impedance 50/75/HiZ K Ohms
(single ended)
50/75
HiZ
Z
—
—
—
—
—
—
Ohms
dB
TX-OI-SE
R
Return loss (with package)
9
LTX-RL
1. All measurements are with 50 ohm impedance.
2. See technical note TN1124, LatticeECP2/M SERDES/PCS Usage Guide for actual binary settings and the min-max range.
Table 3-8. Channel Output Jitter
Description
Deterministic
Frequency
3.125 Gbps
Min.
—
—
—
—
—
—
—
—
—
—
—
—
Typ.
0.08
0.22
0.33
0.05
0.17
0.24
0.03
0.10
0.15
0.04
0.12
0.15
Max.
0.12
0.38
0.43
0.11
0.30
0.39
0.11
0.18
0.29
0.17
0.13
0.29
Units
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
Random
Total
3.125 Gbps
3.125 Gbps
2.5Gbps
Deterministic
Random
Total
2.5Gbps
2.5Gbps
Deterministic
Random
Total
1.25 Gbps
1.25 Gbps
1.25 Gbps
250 Mbps
250 Mbps
250 Mbps
Deterministic
Random
Total
Note: Values are measured with PRBS 27-1, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, reference clock @
10X mode.
3-38
LATTICE [ LATTICE SEMICONDUCTOR ]
