DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2/M sysCONFIG Port Timing Specifications (Continued)
Over Recommended Operating Conditions
Parameter
Description
SOSPI Data Setup Time Before CCLK
SOSPI Data Hold Time After CCLK
Min.
Max.
—
Units
ns
t
t
7
2
SUSPI
—
ns
HSPI
Timing v.A 0.11
Parameter
Min.
Selected value - 30%
40
Max.
Selected value + 30%
60
Units
MHz
%
Master Clock Frequency
Duty Cycle
Timing v.A 0.11
Figure 3-14. sysCONFIG Parallel Port Read Cycle
tBSCYC
tBSCH
tBSCL
CCLK
tSUCS
tHCS
CS1N
CSN
tSUWD
tHWD
WRITEN
tDCB
BUSY
tCORD
Byte 1
Byte 0
Byte 2
Byte n*
D[0:7]
*n = last byte of read cycle.
Figure 3-15. sysCONFIG Parallel Port Write Cycle
tBSCL
tBSCH
CCLK
tSUCS
tHCS
CS1N
CSN
tSUWD
tHWD
WRITEN
tDCB
BUSY
tHCBDI
Byte 1
tSUCBDI
Byte 0
Byte 2
Byte n*
D[0:7]
*n = last byte of write cycle.
3-45
LATTICE [ LATTICE SEMICONDUCTOR ]
