DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
DLL Timing
Over Recommended Operating Conditions
Parameter
Description
Min.
100
100
100
25
Typ.
—
Max.
500
500
500
500
250
250
Units
MHz
f
f
f
f
t
t
Input reference clock frequency (on-chip or off-chip)
Feedback clock frequency (on-chip or off-chip)
Output clock frequency, CLKOP
REF
—
MHz
FB
1
2
—
MHz
CLKOP
CLKOS
PJIT
Output clock frequency, CLKOS
—
MHz
Output clock period jitter (clean input)
Output clock cycle to cycle jitter (clean input)
—
ps p-p
ps p-p
CYJIT
Output clock duty cycle (at 50% levels, 50% duty cycle input clock,
50% duty cycle circuit turned off, time reference delay mode)
t
35
40
65
60
%
%
DUTY
Output clock duty cycle (at 50% levels, arbitrary duty cycle input
clock, 50% duty cycle circuit enabled, time reference delay mode)
t
DUTYTRD
DUTYCIR
Output clock duty cycle (at 50% levels, arbitrary duty cycle input
clock, 50% duty cycle circuit enabled, clock injection removal
mode)
t
t
40
—
60
%
Output clock to clock skew between two outputs with the same
phase setting
3
—
100
ps
SKEW
t
t
Input clock minimum pulse width high (at 80% level)
Input clock minimum pulse width low (at 20% level)
Input clock rise and fall time (20% to 80% levels)
Input clock period jitter
750
750
—
—
—
—
—
—
42
6
—
—
ps
ps
PWH
PWL
t , t
—
1
ns
R
F
t
t
t
t
t
t
—
+/-250
—
ps
INSTB
LOCK
RSWD
PA
DLL lock time
18,500
3
cycles
ns
Digital reset minimum pulse width (at 80% level)
Delay step size
—
16.5
2.376
9.504
59.4
8.553
34.214
ps
Max. delay setting for single delay block (144 taps)
Max. delay setting for four chained delay blocks
ns
RANGE1
24
ns
RANGE4
1. CLKOP runs at the same frequency as the input clock.
2. CLKOS minimum frequency is obtained with divide by 4.
3. This is intended to be a “path-matching” design guideline and is not a measurable specification.
Timing v.A 0.11
3-37
LATTICE [ LATTICE SEMICONDUCTOR ]
