Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2 Power Supply and NC
Signals
VCC
144 TQFP3
208 PQFP3
256 fpBGA4
484 fpBGA4
16, 22, 29, 48, 54, 83, 12, 19, 28, 40, 74, 80, LFE2-6: G7, G9, G10, LFE2-12/LFE2-20: N6, N18, J10,
94, 102, 128, 135
97, 116, 129, 140, 146, H7, J10, K10, K8
171, 188, 198
J11, J12, J13, K14, K9, L14, L9,
M14, M9, N14, N9, P10, P11, P12,
P13
LFE2-12/LFE2-20: G7,
G9, G10, H7, J10, K10,
K8
LFE2-35/LFE2-50: J10, J11, J12,
J13, K14, K9, L14, L9, M14, M9,
N14, N9, P10, P11, P12, P13
VCCIO0
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCJ
139
195, 206
162, 170
143, 148
123, 135
93, 100
55, 63
C5, E7
C12, E10
E14, G12
K12, M14
M10, P12
M7, P5
K5, M3
E3, G5
T15
G10, G9, H8, H9
G11, G12, G13, G14
H14, H15, J15, K16
L16, M16, N16, P16
R14, T12, T13, T14
R9, T10, T11, T9
N7, P7, P8, R8
J8, K7, L7, M7
P15, R15
117
106
89
64
42
31
38, 44
9
10, 14
85
113, 118
51
35
K7
T8
VCCAUX
6, 39, 90, 142
7, 30, 70, 86, 125, 151, G8, H10, J7, K9
174, 190
G5, K5, R5, V7, V11, V8, V13, V15,
M17, P17, E17, G18, D11, F13,
C5, E6
VCCPLL
GND1
None
None
None
LFE2-12/LFE2-20: None
LFE2-35: N6, N18
LFE2-50: N6, N18, K6, J16
11, 21, 30, 47, 51, 61, 5, 13, 17, 25, 32, 42, 60, A1, A16, B12, B5, C8, A22, AA19, AA4, AB1, AB22, B19,
81, 95, 105, 120, 133, 68, 77, 81, 89, 102, 115, E15, E2, H14, H8, H9, B4, C14, C9, D2, D21, F17, F6,
138
122, 139, 145, 159, 169, J3, J8, J9, M15, M2, P9, H10, H11, H12, H13, J14, J20, J3,
175, 184, 192, 201
R12, R5, T1, T16
J9, K10, K11, K12, K13, K15, K8,
L10, L11, L12, L13, L15, L8, M10,
M11, M12, M13, M15, M8, N10,
N11, N12, N13, N15, N8, P14,
P20, P3, P9, R10, R11, R12, R13,
U17, U6, W2, W21, Y14, Y9, A1
NC2
LFE2-6: 45, 46, 124,
None
LFE2-6: K6, R3, P4
LFE2-12: E3, F3, F1, H4, F2, H5,
G1, G3, G2, G4, K6, N1, M2, N2,
M1, N3, N5, N4, P5, N19, M19,
J22, L22, H22, K22, J16, D22,
F21, E21, E22, H19, G20, G19,
F20, C21, C22, H6, J6, H3, H2,
H17, H16, H20, H18
127
LFE2-12/LFE2-20:
None
LFE2-12: 127
LFE2-20/LFE2-35: K6, J16, H6,
J6, H3, H2, H17, H16, H20, H18
LFE2-50: None
1. All grounds must be electrically connected at the board level. For fpBGA packages, the total number of GND balls is less than the actual
number of GND logic connections from the die to the common package GND plane.
2. NC pins should not be connected to any active signals, VCC or GND.
3. Pin orientation follows the conventional order from the pin 1 marking of the top side view and counter-clockwise.
4. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order
ascending horizontally.
4-16
LATTICE [ LATTICE SEMICONDUCTOR ]
