Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
PICs Associated with
DQS Strobe
DDR Strobe (DQS) and
Data (DQ) Pins
PIO Within PIC
For Left and Right Edges of the Device
A
DQ
DQ
P[Edge] [n-4]
B
A
DQ
P[Edge] [n-3]
B
DQ
A
DQ
P[Edge] [n-2]
B
DQ
A
DQ
P[Edge] [n-1]
B
DQ
A
[Edge]DQSn
DQ
P[Edge] [n]
B
A
DQ
P[Edge] [n+1]
B
DQ
A
DQ
P[Edge] [n+2]
B
DQ
A
DQ
P[Edge] [n+3]
B
DQ
For Bottom Edge of the Device
A
DQ
DQ
P[Edge] [n-4]
B
A
DQ
P[Edge] [n-3]
B
DQ
A
DQ
P[Edge] [n-2]
B
DQ
A
DQ
P[Edge] [n-1]
B
DQ
A
[Edge]DQSn
DQ
P[Edge] [n]
B
A
DQ
P[Edge] [n+1]
B
DQ
A
DQ
P[Edge] [n+2]
B
DQ
A
DQ
P[Edge] [n+3]
B
DQ
A
DQ
P[Edge] [n+4]
B
DQ
Notes:
1. “n” is a row PIC number.
2. The DDR interface is designed for memories that support one DQS strobe up to 15 bits
of data for the left and right edges and up to 17 bits of data for the bottom edge. In some
packages, all the potential DDR data (DQ) pins may not be available. PIC numbering
definitions are provided in the “Signal Names” column of the Signal Descriptions table.
4-4
LATTICE [ LATTICE SEMICONDUCTOR ]
