Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Signal Descriptions (Cont.)
Signal Name
I/O
Description
DQ input/output pads: T (top), R (right), B (bottom), L (left), DQS, num = ball
function number.
[LOC]DQS[num]
I/O
I/O
DQ input/output pads: T (top), R (right), B (bottom), L (left), DQ, associated
DQS number.
[LOC]DQ[num]
Test and Programming (Dedicated Pins)
Test Mode Select input, used to control the 1149.1 state machine. Pull-up is
enabled during configuration.
TMS
I
I
Test Clock input pin, used to clock the 1149.1 state machine. No pull-up
enabled.
TCK
Test Data in pin. Used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence). Pull-up is enabled during configuration.
TDI
I
TDO
O
Output pin. Test Data Out pin used to shift data out of a device using 1149.1.
Power supply pin for JTAG Test Access Port.
VCCJ
—
Configuration Pads (Used During sysCONFIG)
Mode pins used to specify configuration mode values latched on rising edge
of INITN. During configuration, a pull-up is enabled. These are dedicated
pins.
CFG[2:0]
I
Open Drain pin. Indicates the FPGA is ready to be configured. During config-
uration, a pull-up is enabled. It is a dedicated pin.
INITN
I/O
I
Initiates configuration sequence when asserted low. This pin always has an
active pull-up. This is a dedicated pin.
PROGRAMN
DONE
Open Drain pin. Indicates that the configuration sequence is complete, and
the startup sequence is in progress. This is a dedicated pin.
I/O
CCLK
I/O Configuration Clock for configuring an FPGA in sysCONFIG mode.
I/O Read control command in SPI or SPIm mode.
BUSY/SISPI
sysCONFIG chip select (active low). During configuration, a pull-up is
enabled.
CSN
I
sysCONFIG chip select (active low). During configuration, a pull-up is
enabled.
CS1N
I
WRITEN
I
Write Data on Parallel port (active low).
sysCONFIG Port Data I/O for Parallel mode.
D[0]/SPIFASTN
I/O
sysCONFIG Port Data I/O for SPI or SPIm. When using the SPI or SPIm
mode, this pin should either be tied high or low, must not be left floating.
D[1:6]
I/O sysCONFIG Port Data I/O for Parallel
D[7]/SPID0
I/O sysCONFIG Port Data I/O for Parallel, SPI, SPIm
Output for serial configuration data (rising edge of CCLK) when using
sysCONFIG port.
DOUT/CSON
O
Input for serial configuration data (clocked with CCLK) when using sysCON-
I/O FIG port. During configuration, a pull-up is enabled. Output when used in SPI/
SPIm modes.
DI/CSSPI0N
Dedicated SERDES Signals1, 2, 3
Termination resistor switching power (3.3V). This pin must be tied to 3.3V
even if the quad is unused.
[LOC]_SQ_VCCAUX33
—
[LOC]_SQ_REFCLKN
[LOC]_SQ_REFCLKP
I
I
Negative Reference Clock Input
Positive Reference Clock Input
PLL and Reference clock buffer power (1.2V). This pin must be tied to 1.2V
even if the quad is unused.
[LOC]_SQ_VCCP
—
4-2
LATTICE [ LATTICE SEMICONDUCTOR ]
