LatticeECP2/M Family Data Sheet
Pinout Information
August 2008
Data Sheet DS1006
Signal Descriptions
Signal Name
I/O
Description
General Purpose
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or B (Bottom), only need to spec-
ify Row Number. When Edge is L (Left) or R (Right), only need to specify Col-
umn Number.
P[Edge] [Row/Column Number*]_[A/B]
I/O
[A/B] indicates the PIO within the PIC to which the pad is connected. Some of
these user-programmable pins are shared with special function pins. These
pins, when not used as special purpose pins, can be programmed as I/Os for
user logic. During configuration the user-programmable I/Os are tri-stated
with an internal pull-up resistor enabled. If any pin is not used (or not bonded
to a package pin), it is also tri-stated with an internal pull-up resistor enabled
after configuration.
GSRN
NC
I
Global RESET signal (active low). Any I/O pin can be GSRN.
No connect.
—
—
—
GND
Ground. Dedicated pins.
V
V
V
V
Power supply pins for core logic. Dedicated pins.
CC
Auxiliary power supply pin. This dedicated pin powers all the differential and
referenced input buffers.
—
—
—
CCAUX
CCIOx
CCPLL
Dedicated power supply pins for I/O bank x.
PLL supply pins. Should be tied to V even when the corresponding PLL is
CC
unused.
Reference supply pins for I/O bank x. Pre-determined pins in each bank are
V
, V
—
REF1_x REF2_x
assigned as V
inputs. When not used, they may be used as I/O pins.
REF
XRES4
PLLCAP4
—
—
10K ohm +/-1% resistor must be connected between this pad and ground.
External capacitor connection for PLL.
PLL, DLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)
[LOC][num]_V
—
Power supply pin for PLL: ULM, LLM, URM, LRM, num = row from center.
CCPLL
General Purpose PLL (GPLL) input pads: ULM, LLM, URM, LRM, num = row
from center, T = true and C = complement, index A,B,C...at each side.
[LOC][num]_GPLL[T, C]_IN_A
[LOC][num]_GPLL[T, C]_FB_A
[LOC][num]_SPLL[T, C]_IN_A
[LOC][num]_SPLL[T, C]_FB_A
[LOC][num]_DLL[T, C]_IN_A
[LOC][num]_DLL[T, C]_FB_A
PCLK[T, C]_[n:0]_[3:0]
I
Optional feedback GPLL input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
I
I
I
I
I
I
Secondary PLL (SPLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Optional feedback (SPLL) input pads: ULM, LLM, URM, LRM, num = row
from center, T = true and C = complement, index A,B,C...at each side.
DLL input pads: ULM, LLM, URM, LRM, num = row from center, T = true and
C = complement, index A,B,C...at each side.
Optional feedback (DLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Primary Clock pads, T = true and C = complement, n per side, indexed by
bank and 0,1,2,3 within bank.
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DS1006 Pinout Information_01.9
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