DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Switching Test Conditions
Figure 3-23 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 3-18.
Figure 3-22. Output Test Load, LVTTL and LVCMOS Standards
VT
R1
DUT
Test Point
R2
CL*
*CL Includes Test Fixture and Probe Capacitance
Table 3-18. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition
R
R
C
Timing Ref.
V
T
1
2
L
LVCMOS 3.3 = 1.5V
—
—
—
—
—
—
LVCMOS 2.5 = V
LVCMOS 1.8 = V
LVCMOS 1.5 = V
LVCMOS 1.2 = V
/2
/2
/2
/2
CCIO
CCIO
CCIO
CCIO
LVTTL and other LVCMOS settings (L -> H, H -> L)
0pF
∞
∞
LVCMOS 2.5 I/O (Z -> H)
LVCMOS 2.5 I/O (Z -> L)
LVCMOS 2.5 I/O (H -> Z)
LVCMOS 2.5 I/O (L -> Z)
∞
1MΩ
∞
1MΩ
∞
V
V
V
V
/2
/2
CCIO
CCIO
V
V
CCIO
100
- 0.10
+ 0.10
—
OH
OL
100
∞
CCIO
Note: Output test conditions for all other interfaces are determined by the respective standards.
3-49
LATTICE [ LATTICE SEMICONDUCTOR ]
