DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
JTAG Port Timing Specifications
Over Recommended Operating Conditions
Symbol
Parameter
Min
—
40
20
20
8
Max
25
—
Units
MHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
TCK clock frequency
MAX
TCK [BSCAN] clock pulse width
BTCP
TCK [BSCAN] clock pulse width high
—
ns
BTCPH
BTCPL
BTS
TCK [BSCAN] clock pulse width low
—
ns
TCK [BSCAN] setup time
—
ns
TCK [BSCAN] hold time
10
50
—
—
—
8
—
ns
BTH
TCK [BSCAN] rise/fall time
—
mV/ns
ns
BTRF
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to valid disable
TAP controller falling edge of clock to valid enable
BSCAN test capture register setup time
10
10
10
—
BTCO
ns
BTCODIS
BTCOEN
BTCRS
BTCRH
BUTCO
BTUODIS
BTUPOEN
ns
ns
BSCAN test capture register hold time
25
—
—
—
—
ns
BSCAN test update register, falling edge of clock to valid output
BSCAN test update register, falling edge of clock to valid disable
BSCAN test update register, falling edge of clock to valid enable
25
25
25
ns
ns
ns
Timing v.A 0.11
Figure 3-21. JTAG Port Timing Waveforms
TMS
TDI
t
t
BTH
BTS
t
t
t
BTCP
BTCPL
BTCPH
TCK
TDO
t
t
BTCODIS
t
BTCO
BTCOEN
Valid Data
Valid Data
t
BTCRH
t
BTCRS
Data to be
captured
from I/O
Data Captured
t
t
t
BTUPOEN
BUTCO
BTUODIS
Data to be
driven out
to I/O
Valid Data
Valid Data
3-48
LATTICE [ LATTICE SEMICONDUCTOR ]
