DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Figure 3-16. sysCONFIG Slave Serial Port Timing
tSSCL
tSSCH
CCLK (input)
tHSCDI
tSUSCDI
DIN
DOUT
tCODO
Figure 3-17. Power-On-Reset (POR) Timing
V
V
/ V
/
CC
CCIO8
CCAUX
1
tICFG
INITN
DONE
CCLK 2
tVMC
CFG[2:0] 3
Valid
1. Time taken from V , V
or V
, whichever is the last to cross the POR trip point.
CC CCAUX
CCIO8
2. Device is in a Master Mode (SPI, SPIm).
3. The CFG pins are normally static (hard wired).
Figure 3-18. Configuration from PROGRAMN Timing
tPRGMRJ
PROGRAMN
tDINIT
tDPPINIT
INITN
tDINITD
DONE
CCLK
CFG[2:0]1
Valid
tIODISS
USER I/O
1. The CFG pins are normally static (hard wired)
3-46
LATTICE [ LATTICE SEMICONDUCTOR ]
