IS43R16320B
IC43R16320B
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
DM
WRIT
NOP
READ
NOP
2 cycle
CL=3
High-Z
High-Z
DQ
in0 in1
in2
in3
out0 out1 out2 out3
DQS
Data masked
BL = 4
CL = 3
[WRITE to READ delay = 2 clock cycle]
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
WRIT
NOP
3 cycle
READ
NOP
CL=3
tWTR*
DM
out0 out1 out2 out3
DQ
in0 in1
in2
in3
DQS
BL = 4
CL = 3
Data masked
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
[WRITE to READ delay = 3 clock cycle]
36
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
06/11/08