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IC43R16320B-6TL 参数 Datasheet PDF下载

IC43R16320B-6TL图片预览
型号: IC43R16320B-6TL
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.7ns, CMOS, PDSO66, ROHS COMPLIANT, PLASTIC, TSOP2-66]
分类和应用: 动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 48 页 / 839 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IS43R16320B  
IC43R16320B  
A Read command to the consecutive Write command interval with the BST command  
Destination row of the consecutive write  
command  
Bank  
address  
Row address State  
Operation  
Issue the BST command. tBSTW (tBSTZ) after the BST command, the  
consecutive write command can be issued.  
1. Same  
Same  
Different  
Any  
ACTIVE  
Precharge the bank to interrupt the preceding read operation. tRP after the  
precharge command, issue the ACT command. tRCD after the ACT command, the  
consecutive write command can be issued. See ‘A read command to the  
consecutive precharge interval’ section.  
2. Same  
Issue the BST command. tBSTW (tBSTZ) after the BST command, the  
consecutive write command can be issued.  
3. Different  
ACTIVE  
IDLE  
Precharge the bank independently of the preceding read operation. tRP after the  
precharge command, issue the ACT command. tRCD after the ACT command, the  
consecutive write command can be issued.  
t0  
t1  
t2  
t3  
t4  
t5  
t6  
t7  
t8  
CK  
/CK  
Command  
READ  
WRIT  
BST  
NOP  
NOP  
tBSTW (tBSTZ)  
DM  
tBSTZ (= CL)  
DQ  
out0 out1  
in0 in1 in2 in3  
High-Z  
DQS  
OUTPUT  
INPUT  
BL = 4  
CL = 3  
READ to WRITE Command Interval  
Integrated Silicon Solution, Inc. — www.issi.com  
33  
Rev. 00B  
06/11/08  
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