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IC43R16320B-6TL 参数 Datasheet PDF下载

IC43R16320B-6TL图片预览
型号: IC43R16320B-6TL
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.7ns, CMOS, PDSO66, ROHS COMPLIANT, PLASTIC, TSOP2-66]
分类和应用: 动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 48 页 / 839 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IS43R16320B  
IC43R16320B  
Bank active command interval  
Destination row of the consecutive ACT  
command  
Bank  
Row address  
address  
1. Same  
2. Different  
State  
Operation  
Two successive ACT commands can be issued at tRC interval. In between two  
successive ACT operations, precharge command should be executed.  
Any  
Any  
ACTIVE  
Precharge the bank. tRP after the precharge command, the consecutive ACT  
command can be issued.  
ACTIVE  
IDLE  
tRRD after an ACT command, the next ACT command can be issued.  
CK  
/CK  
Command  
ACT
ACT  
NOP  
PRE  
NOP  
ACT  
NOP  
Address  
BA  
ROW: 0  
ROW: 1  
ROW: 0  
Bank0  
Active  
Bank3  
Active  
Bank0  
Precharge  
Bank0  
Active  
tRRD  
tRC  
Bank Active to Bank Active  
Mode register set to Bank-active command interval  
The interval between setting the mode register and executing a bank-active command must be no less than tMRD.  
CK  
/CK  
Command  
MRS  
NOP  
ACT  
NOP  
Address  
CODE  
BS and ROW  
Mode Register Set  
Bank3  
Active  
tMRD  
Integrated Silicon Solution, Inc. — www.issi.com  
39  
Rev. 00B  
06/11/08  
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