IS43R16320B
IC43R16320B
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 2.5V 0.2V, VSS, VSSQ = 0V) [DDR333, 266]
-6
-7
min.
7.5
max.
12
min.
7.5
max.
12
Parameter
Symbol
tCK
Unit Notes
Clock cycle time
(CL = 2)
ns
10
(CL = 2.5)
tCK
tCH
tCL
6
12
7.5
12
ns
CK high-level width
CK low-level width
0.45
0.55
0.55
tCK
tCK
0.45
0.45
min
0.55
0.55
0.45
min
(tCH, tCL)
CK half period
tHP
—
—
tCK
ns
(tCH, tCL)
DQ output access time from CK, /CK tAC
–0.7
0.7
0.6
0.45
–0.75
0.75
2, 11
2, 11
3
DQS output access time from CK,
/CK
tDQSCK –0.6
tDQSQ
ns
–0.75
—
0.75
0.5
DQS to DQ skew
—
ns
ns
ns
DQ/DQS output hold time from DQS tQH
tHP – tQHS —
tHP – tQHS —
Data hold skew factor
tQHS
—
—
0.55
0.7
—
—
0.75
Data-out high-impedance time from
CK, /CK
tHZ
tLZ
ns
ns
5, 11
6, 11
0.75
0.75
Data-out low-impedance time from
CK, /CK
–0.7
0.7
–0.75
Read preamble
tRPRE
tRPST
tDS
0.9
1.1
0.6
—
tCK
tCK
ns
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
Read postamble
0.4
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
0.45
0.45
1.75
8
8
7
tDH
—
—
ns
tDIPW
—
—
ns
tWPRES 0
—
—
ns
tWPRE 0.25
tWPST 0.4
—
0.25
0.4
tCK
tCK
—
Write postamble
0.6
0.6
9
Write command to first DQS latching
transition
0.75
1.25
tDQSS
tDSS
0.75
1.25
tCK
DQS falling edge to CK setup time
0.2
—
—
0.2
—
—
—
—
tCK
tCK
tCK
tCK
DQS falling edge hold time from CK tDSH
0.2
0.2
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
0.35
0.35
—
—
0.35
0.35
Address and control input setup time tIS
0.75
—
0.9
—
ns
8
Address and control input hold time tIH
Address and control input pulse width tIPW
0.75
2.2
—
—
0.9
2.2
—
—
ns
ns
8
7
Mode register set command cycle
time
tMRD
2
—
2
—
tCK
ns
Active to Precharge command period tRAS
42
60
120000
—
45
65
120000
—
Active to Active/Auto-refresh
tRC
ns
command period
Auto-refresh to Active/Auto-refresh
command period
tRFC
72
—
75
ns
—
Active to Read/Write delay
tRCD
18
—
—
—
—
20
—
—
—
—
ns
ns
ns
ns
Precharge to active command period tRP
18
20
Active to Autoprecharge delay
Active to active command period
tRAP
tRRD
tRCD min.
12
tRCDmin.
15
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
06/11/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
