IS43R16320B
IC43R16320B
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycle.
10. Command/Address stable at ≥ VIH or ≤ VIL.
DC Characteristics 2 (TA = 0°C to +70°C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V) [DDR400]
(TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333, 266]
Parameter
Symbol
ILI
min.
–2
max.
2
Unit
µA
Test condition
Notes
Input leakage current
Output leakage current
Output high current
Output low current
VDD ≥ VIN ≥ VSS
VDDQ ≥ VOUT ≥ VSS
VOUT = 1.95V
ILO
–5
5
µA
IOH
IOL
–15.2
15.2
—
—
mA
mA
VOUT = 0.35V
Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V) [DDR400]
(TA = +25°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333, 266]
Parameter
Symbol
CI1
Pins
min.
2.0
2.0
—
typ.
—
—
—
—
—
—
max.
3.0
3.0
0.25
0.5
5
Unit
pF
pF
pF
pF
pF
pF
Notes
Input capacitance
CK, /CK
1
CI2
All other input pins
CK, /CK
1
Delta input capacitance
Cdi1
Cdi2
CI/O
Cdio
1
All other input-only pins
DQ, DM, DQS
DQ, DM, DQS
—
1
Data input/output capacitance
Delta input/output capacitance
4.0
—
1, 2
1
0.5
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ΔVOUT = 0.2V.
2. DOUT circuits are disabled.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
06/11/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
