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IC43R16320B-6TL 参数 Datasheet PDF下载

IC43R16320B-6TL图片预览
型号: IC43R16320B-6TL
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.7ns, CMOS, PDSO66, ROHS COMPLIANT, PLASTIC, TSOP2-66]
分类和应用: 动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 48 页 / 839 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IS43R16320B  
IC43R16320B  
Timing Parameter Measured in Clock Cycle  
Number of clock cycle  
5ns  
tCK  
6ns  
7.5ns  
min.  
Parameter  
Symbol  
tWPD  
min.  
max.  
min.  
max.  
max.  
Unit  
tCK  
Write to pre-charge command delay  
(same bank)  
1 + BL/2  
+ tWR  
1 + BL/2  
+ tWR  
1 + BL/2  
+ tWR  
Read to pre-charge command delay  
(same bank)  
tRPD  
BL/2  
BL/2  
BL/2  
tCK  
tCK  
Write to read command delay  
(to input all data)  
1 + BL/2  
+ tWTR  
1 + BL/2  
+ tWTR  
1 + BL/2  
+ tWTR  
tWRD  
Burst stop command to write  
command delay  
tBSTW  
2
tCK  
(CL = 2)  
(CL = 2.5)  
(CL = 3)  
tBSTW  
tBSTW  
3
3
3
3
3
tCK  
tCK  
Burst stop command to DQ High-Z  
(CL = 2)  
tBSTZ  
2
2
tCK  
(CL = 2.5)  
(CL = 3)  
tBSTZ  
tBSTZ  
3
3
2.5  
3
2.5  
3
2.5  
3
2.5  
3
tCK  
tCK  
Read command to write command  
delay (to output all data)  
(CL = 2)  
tRWD  
2 + BL/2  
tCK  
(CL = 2.5)  
(CL = 3)  
tRWD  
tRWD  
3 + BL/2  
3 + BL/2  
3 + BL/2  
3 + BL/2  
tCK  
tCK  
3 + BL/2  
Pre-charge command to High-Z  
(CL = 2)  
tHZP  
2
2
tCK  
(CL = 2.5)  
tHZP  
tHZP  
tWCD  
tWR  
3
3
2.5  
3
2.5  
3
2.5  
3
2.5  
3
tCK  
tCK  
tCK  
tCK  
tCK  
(CL = 3)  
Write command to data in latency  
Write recovery  
1
1
1
1
1
1
3
0
3
0
2
0
DM to data in latency  
tDMD  
0
0
0
Self-refresh exit to non-read  
command  
tSNR  
15  
12  
10  
tCK  
Self-refresh exit to read command  
Power down entry  
tSRD  
200  
1
1
200  
1
1
200  
1
1
tCK  
tCK  
tCK  
tCK  
tPDEN  
Power down exit to command input tPDEX  
Active to Precharge command period tRAS  
1
1
1
8
7
6
Active to Active/Auto-refresh  
tRC  
11  
10  
12  
3
9
tCK  
tCK  
tCK  
tCK  
command period  
Auto-refresh to Active/Auto-refresh  
tRFC  
14  
3
10  
3
command period  
Active to Read/Write delay  
tRCD  
3
Precharge to active command period tRP  
3
3
Integrated Silicon Solution, Inc. — www.issi.com  
13  
Rev. 00B  
06/11/08  
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