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IC43R16320B-6TL 参数 Datasheet PDF下载

IC43R16320B-6TL图片预览
型号: IC43R16320B-6TL
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.7ns, CMOS, PDSO66, ROHS COMPLIANT, PLASTIC, TSOP2-66]
分类和应用: 动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 48 页 / 839 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IS43R16320B  
IC43R16320B  
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 2.6V 0.1V, VSS, VSSQ = 0V) [DDR400]  
-5  
Parameter  
Symbol  
tCK  
min.  
5
max  
8
Unit  
ns  
Notes  
10  
Clock cycle time  
CK high-level width  
CK low-level width  
tCH  
0.45  
0.55  
0.55  
tCK  
tCL  
0.45  
min  
(tCH, tCL)  
tCK  
CK half period  
tHP  
DQ output access time from CK, /CK  
DQS output access time from CK, /CK  
DQS to DQ skew  
tAC  
–0.7  
0.7  
ns  
ns  
ns  
ns  
ns  
2, 11  
2, 11  
3
tDQSCK  
tDQSQ  
tQH  
–0.55  
0.55  
0.4  
DQ/DQS output hold time from DQS  
Data hold skew factor  
tHP – tQHS —  
tQHS  
0.5  
Data-out high-impedance time  
from CK, /CK  
tHZ  
tLZ  
0.7  
0.7  
1.1  
ns  
ns  
5,11  
6,11  
Data-out low-impedance time  
from CK, /CK  
–0.7  
Read preamble  
tRPRE  
tRPST  
tDS  
0.9  
0.4  
0.4  
0.4  
1.75  
0
tCK  
tCK  
ns  
Read postamble  
0.6  
DQ and DM input setup time  
DQ and DM input hold time  
DQ and DM input pulse width  
Write preamble setup time  
Write preamble  
8
8
7
tDH  
ns  
tDIPW  
tWPRES  
tWPRE  
tWPST  
ns  
ns  
0.25  
0.4  
0.72  
0.2  
0.2  
0.35  
0.35  
0.6  
0.6  
2.2  
2
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
ns  
Write postamble  
0.6  
9
Write command to first DQS latching transition tDQSS  
1.28  
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
DQS input high pulse width  
tDSS  
tDSH  
tDQSH  
tDQSL  
tIS  
DQS input low pulse width  
Address and control input setup time  
Address and control input hold time  
Address and control input pulse width  
Mode register set command cycle time  
Active to Precharge command period  
8
8
7
tIH  
ns  
tIPW  
tMRD  
tRAS  
ns  
tCK  
ns  
40  
120000  
Active to Active/Auto-refresh command period tRC  
Auto-refresh to Active/Auto-refresh command  
period  
55  
ns  
tRFC  
70  
ns  
Active to Read/Write delay  
tRCD  
tRP  
15  
15  
ns  
ns  
ns  
ns  
ns  
Precharge to active command period  
Active to Autoprecharge delay  
Active to active command period  
Write recovery time  
tRAP  
tRRD  
tWR  
tRCD min.  
10  
15  
Auto precharge write recovery and precharge  
time  
(tWR/tCK)+  
(tRP/tCK)  
tDAL  
tCK  
13  
Internal write to Read command delay  
Average periodic refresh interval  
tWTR  
tREF  
2
tCK  
µs  
7.8  
Integrated Silicon Solution, Inc. — www.issi.com  
9
Rev. 00B  
06/11/08  
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