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BBT3821 参数 Datasheet PDF下载

BBT3821图片预览
型号: BBT3821
PDF下载: 下载PDF文件 查看货源
内容描述: 八通道2.488Gbps速率为3.187Gbps /重定时器里 [Octal 2.488Gbps to 3.187Gbps/ Lane Retimer]
分类和应用:
文件页数/大小: 75 页 / 1107 K
品牌: INTERSIL [ Intersil ]
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BBT3821  
Table 14. IEEE PACKAGE IDENTIFIER REGISTERS  
MDIO REGISTER ADDRESSES = 1.14:15 (1.000E:F’h)  
BIT  
1.14.15:0  
1.15.15:0  
NAME  
Package ID  
Package ID  
SETTING  
DEFAULT  
R/W  
R/W  
R/W  
DESCRIPTION  
Package OUI bits 3:24 & 00’h  
If NVR is loaded, these are copies of  
1.32818:32819 (1.8032:8033’h) & 1.32820:32821  
(1.8034:8035’h)  
etc.  
00’h  
XENPAK-DEFINED REGISTERS (1.8000’H TO 1.8106’H)  
Table 15. XENPAK NVR CONTROL & STATUS REGISTER  
MDIO (XENPAK) REGISTER ADDRESS = 1.32768 (1.8000’h)  
BIT  
1.32768.15:6  
1.32768.5  
NAME  
Reserved  
SETTING  
DEFAULT  
000’h  
R/W  
R/W  
DESCRIPTION  
(1)  
(2)  
2
NVR Command  
1 = Write NVR  
0 = Read NVR  
0’b  
R/W  
Write/Read Control for I C operation  
1.32768.4  
Reserved  
0’b  
RO  
RO  
1.32768.3:2  
NVR Command  
Current Status of  
NVR Command  
00’b  
11 = Command failed  
(3)  
Status  
10 = Command in progress/Queued  
01 = Command completed with success  
00 = Idle  
(2)  
(3)  
1.32768.1:0  
Extended NVR  
Command  
NVR operation to be 11’b  
performed  
R/W  
10 = read/write one byte  
(3)  
11 = read/write all NVR contents  
Other values = reserved  
Note (1): User writes to these bits are not valid unless the Command Status is Idle. The Command Status will not return to Idle until read after command completion  
(either Succeed or Failed).  
Note (2): At the end of a hardware RESET via the RSTN pin, on powerup, or on a register [1,3,4].0.15 RESET operation, and if the XP_ENA pin is asserted, the  
BBT3821 will automatically begin an ‘all NVR read’ operation.  
Note (3): The single byte commands are controlled through the bits of the registers at 1.32769:32774 (1.8001:8006’h). The ‘block write/read’ commands are affected by  
register 1.32773 (1.8005’h). Additional status is available in 1.327743 (1.8006’h)  
2
Table 16. I C ONE-BYTE OPERATION DEVICE ADDRESS REGISTER  
MDIO REGISTER ADDRESS = 1.32769 (1.8001’h)  
BIT  
1.32769.15:8  
1.32769.7:0  
NAME  
SETTING  
DEFAULT  
00’h  
R/W  
RO  
R/W  
DESCRIPTION  
Reserved  
2
2
Device  
Address  
I C Device address to  
access  
A2’h  
All I C Device addresses are even. Bit 0 cannot be set.  
2
Table 17. I C ONE-BYTE OPERATION MEMORY ADDRESS REGISTER  
MDIO REGISTER, ADDRESS = 1.32770 (1.8002’h)  
BIT  
NAME  
SETTING  
DEFAULT  
R/W  
R/W  
DESCRIPTION  
2
(2)  
2
1.32770.15:0  
Memory  
Address  
I C Memory address to  
access  
0000’h  
I C Memory Address within Device address of 1.32769  
(1.8001’h)  
2
2
Note (1): 8-bit-addressed I C devices are addressed using bits 7:0. Never set bit 1.32773.8 (1.8005’h.8) for 16-bit address operation with an 8-bit address I C device.  
2
Table 18. I C ONE-BYTE OPERATION READ DATA REGISTER  
MDIO REGISTER ADDRESS = 1.32771 (1.8003’h)  
BIT  
1.32771.15:8  
1.32771.7:0  
NAME  
Reserved  
Read Data  
SETTING  
DEFAULT  
00’h  
R/W  
RO  
RO  
DESCRIPTION  
2
2
I C Read Data  
00’h  
Result of I C 1-byte Read operation  
24  
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