BBT3821
another column containing a non-idle is received. If in
8b/10b Coding and Decoding
8 Bit Mode
addition either of the AKR_SM_EN or XAUI_EN bits in the
respective MDIO registers at Addresses [3,4].C001’h is set
(see Table 64 and Table 81, these IDLEs will be sequenced
on transmission into a pseudo-random pattern of ||A||, ||K||,
and ||R|| codes according to the IEEE 802.3ae specified
algorithm. If neither of the AKR_SM_EN and XAUI_EN bits
are set, the internal IDLEs will all be transmitted as /K/
codes. Elasticity will be achieved by adding or deleting
columns of internal IDLEs.
If 8B/10B encoding/decoding is turned on, the nLiten
BBT3821 expects to receive a properly encoded serial bit
stream. The serial bit stream must be ordered “abcdeifghj”
with “a” being the first bit received and “j” the last. If the
received data contains an error, the Retimer will re-transmit it
as an ERROR or /E/ character. The character transmitted
may be controlled via the ERROR code Registers
[3,4].C002’h, Table 66 and Table 82. The internal decoding
into, and encoding from, the FIFOs is listed in Table 1 below.
If the TRANS_EN bit or XAUI_EN bit (MDIO Registers at
addresses [3,4].C001’h, see Table 64 and Table 81 are set,
all incoming XAUI or CX4/LX4 IDLE patterns will be
converted to the (internal) XGMII IDLE pattern set by the
respective PCS or PHY XS control registers at addresses
[3,4].C003’h, with a default value 107’h, the standard XGMII
IDLE code (see Table 67 and Table 83) in the internal FIFOs.
The first full column of IDLES after any column containing a
non-IDLE will be stored in the respective elasticity FIFO, and
all subsequent full IDLE columns will repeat this pattern, until
If neither the TRANS_EN bit nor the XAUI_EN bit is set (for
either the PCS or the PHY XS), the incoming XAUI IDLE
codes will all be decoded to the appropriate XGMII control
code values in the respective internal FIFO. If the AKR_EN
or XAUI_EN bits are set, they will be sequenced into a
pseudo-random pattern of ||A||, ||K||, and ||R|| codes and
retransmitted, if not, the Inter Packet Gap (IPG) will be
retransmitted as the same XAUI codes as in the first full
IDLE column.
For most applications, the XAUI_EN bit high configuration is
the most desirable, and is the default.
Table 1. VALID 10b/8b DECODER & ENCODER PATTERNS
INTERNAL DATA TRANSMITTING SERDES
RECEIVING SERDES
NOTES
_
_
SERIAL CODE, TRANS EN
INTERNAL AKR SM_
SERIAL
SERIAL
CODE
(4)
(4)
CHARACTER
BIT
E-BIT
K-BIT FIFO DATA
EN
CHARACTER
DESCRIPTION
Valid Data
X
0
0
0-FF’h
X
See 802.3
Table
Valid Data Same Data Value as Received
(2)
/K/ (Sync) K28.5
/A/ (Align) K28.3
/R/ (Skip) K28.0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
07’h
1
0
/A/ /K/ /R/
/K/
IEEE802.3ae algorithm
(1)
BC
K28.5
K28.3
Comma (Sync)
IEEE802.3ae algorithm
Align
(2)
1
07’h
1
/A/ /K/ /R/
/A/
(1)
0
7C
0
(2)
1
07’h
1
/A/ /K/ /R/
/R/
IEEE802.3ae algorithm
Alternate Idle (Skip)
Start
(1)
0
1C
0
K28.0
K27.7
K29.7
K28.1
K28.2
K28.4
K28.6
K28.7
K23.7
K30.7
/S/ K27.7
/T/ K29.7
K28.1
X
X
X
X
X
X
X
X
X
X
FB
FD
3C
5C
9C
DC
FC
F7
1
/S/
0
/T/
Terminate
X
X
X
X
X
X
X
X
Extra comma
/F/ K28.2
/Q/ K28.4
K28.6
/F/
Signal Ordered_Set
Sequence Ordered_Set
/Q/
K28.7
Repeat has False Comma
K23.7
/E/ K30.7
Any other
FE
(3)
/E/
Error Code
Error Code
= ERROR reg.
Invalid code
Note (1): First incoming IDLE only, subsequent IDLEs in that block repeat first received code.
Note (2): Default value, actually set by ‘Internal Idle’ register, [3:4].C003’h, see Table 67 and Table 83.
Note (3): Value set by ‘ERROR Code’ register, [3:4].C002’h, see Table 66 and Table 66. The XAUI_EN bit forces it to 1FE’h.
Note (4): If the XAUI_EN bit is set, the BBT3821 acts as though both the TRANS_EN and AKR_EN bits are set.
12
INTERSIL [ Intersil ]
