BBT3821
FIGURE 2. DETAILED FUNCTIONAL BLOCK DIAGRAM (BIST OMITTED)
(See also Figure 4 & Figure 5 for MDIO and LASI blocks and Figure 6 for BIST operation)
20X or 10X
Clock
MDIO
2
XAUI
LX4/CX4
I C
BIST
JTAG
MDIO Register, LASI & Common Logic
Engine
Equalizer
Signal
Detect
RX FIFO
Deskew
TXFIFO &
Error and
Orderset
Detector
8B/10B
Encoder,
AKR
RXP0P/N
TCX0 P/N
TCX1 P/N
10B/8B
Decoder
CDR
CDR
Generator
Equalizer
Signal
Detect
RX FIFO
Deskew
TXFIFO &
Error and
Orderset
Detector
8B/10B
Encoder,
AKR
RXP1P/N
RXP2P/N
10B/8B
Decoder
Generator
Egress
Egress
Equalizer
Signal
Detect
RX FIFO
Deskew
TXFIFO &
Error and
Orderset
Detector
8B/10B
Encoder,
AKR
TCX2 P/N
10B/8B
Decoder
CDR
CDR
Generator
Equalizer
Signal
Detect
RX FIFO
Deskew
TXFIFO &
Error and
Orderset
Detector
8B/10B
Encoder,
AKR
RXP3P/N
TCX3 P/N
10B/8B
Decoder
PCS //
(PHY XS)
Loopback
Generator
PMA
Loop
back
PHY XS
(Serial)
Loopback
PCS // Network
Loopback
RX FIFO
Deskew
8B/10B
TXFIFO &
10B/8B
Decoder
TXP0 P/N
Equalizer
Signal
Detect
Encoder,
AKR
Error and
Orderset
Detector
CDR
RCX0 P/N
RCX1 P/N
Generator
RX FIFO
Deskew
8B/10B
Encoder,
AKR
TXFIFO &
Error and
Orderset
Detector
10B/8B
Decoder
TXP1 P/N
Equalizer,
Signal
Detect
CDR
CDR
Generator
Ingress
Ingress
RX FIFO
Deskew
TXFIFO &
Error and
Orderset
Detector
8B/10B
Encoder,
AKR
TXP2 P/N
TXP3 P/N
10B/8B
Decoder
Equalizer,
Signal
Detect
RCX2 P/N
RCX3 P/N
Generator
RX FIFO
Deskew
8B/10B
Encoder,
AKR
TXFIFO &
Error and
Orderset
Detector
10B/8B
Decoder
Equalizer,
Signal
Detect
CDR
Generator
Device Address 1 PMA/PMD
Device Address 4 PHY XGXS
Device Address 3 PCS
8
INTERSIL [ Intersil ]
