82C59A
Pinouts
82C59A (PDIP, CERDIP, SOIC)
82C59A (PLCC, CLCC)
TOP VIEW
TOP VIEW
1
2
3
4
28 V
CS
WR
RD
CC
27
26
25
24
23
22
21
20
19
18
17
16
15
A0
1
4
3
2
28 27 26
INTA
IR7
25
24
23
22
D6
D5
D4
D3
D2
D1
D0
IR7
IR6
IR5
IR4
5
6
D7
IR6
D6
5
6
7
8
9
IR5
D5
7
8
IR4
D4
IR3
21 IR3
D3
9
IR2
D2
10
11
20
19
IR2
IR1
10
11
12
13
14
IR1
D1
IR0
D0
12
13 14 15 16 17 18
INT
CAS 0
CAS 1
GND
SP/EN
CAS 2
PIN
DESCRIPTION
Data Bus (Bidirectional)
Read Input
D7 - D0
RD
WR
Write Input
A0
Command Select Address
Chip Select
CS
CAS 2 - CAS 0
SP/EN
INT
Cascade Lines
Slave Program Input Enable
Interrupt Output
INTA
Interrupt Acknowledge Input
Interrupt Request Inputs
IR0 - IR7
Functional Diagram
INTA
INT
DATA
BUS
BUFFER
D -D
7
0
CONTROL LOGIC
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
RD
WR
READ/
WRITE
LOGIC
IN -
SERVICE
REG
(ISR)
INTERRUPT
REQUEST
REG
PRIORITY
RESOLVER
A
0
(IRR)
CS
CAS 0
CAS 1
CAS 2
CASCADE
BUFFER
COMPARATOR
INTERRUPT MASK REG
(IMR)
SP/EN
INTERNAL BUS
FIGURE 1.
4-2
INTERSIL [ Intersil ]
