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Intel Advanced+ Boot Block Flash Memory (C3)
6.0
Power Consumption
Intel Flash devices have a tiered approach to power savings that can significantly reduce overall
system power consumption. The Automatic Power Savings (APS) feature reduces power
consumption when the device is selected but idle. If CE# is deasserted, the flash enters its standby
mode, where current consumption is even lower. If RP# is deasserted, the flash enter deep power-
down mode for ultra-low current consumption. The combination of these features can minimize
memory power consumption, and therefore, overall system power consumption.
6.1
6.2
6.3
Active Power (Program/Erase/Read)
With CE# at a logic-low level and RP# at a logic-high level, the device is in the active mode. Refer
to the DC Characteristic tables for I current values. Active power is the largest contributor to
CC
overall system power consumption. Minimizing the active current could have a profound effect on
system power consumption, especially for battery-operated devices.
Automatic Power Savings (APS)
Automatic Power Savings provides low-power operation during read mode. After data is read from
the memory array and the address lines are idle, APS circuitry places the device in a mode where
typical current is comparable to I
new location is read.
. The flash stays in this static state with outputs valid until a
CCS
Standby Power
When CE# is at a logic-high level (V ), the flash memory is in standby mode, which disables
IH
much of the device’s circuitry and substantially reduces power consumption. Outputs are placed in
a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logic-
high level during Erase or Program operations, the device will continue to perform the operation
and consume corresponding active power until the operation is completed.
System engineers should analyze the breakdown of standby time versus active time, and quantify
the respective power consumption in each mode for their specific application. This approach will
provide a more accurate measure of application-specific power and energy requirements.
6.4
Deep Power-Down Mode
The deep power-down mode is activated when RP# = V . During read modes, RP# going low de-
IL
selects the memory and places the outputs in a high-impedance state. Recovery from deep power-
down requires a minimum time of t
operations.
for Read operations, and t
/t
for Write
PHQV
PHWL PHEL
32
Datasheet
INTEL [ INTEL ]
