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Intel Advanced+ Boot Block Flash Memory (C3)
5.5.1
5.5.2
Reading the Protection Register
The protection register is read in the read-identifier mode. The device is switched to this mode by
issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses shown
in Figure 6, “Protection Register Mapping” retrieve the specified information. To return to read-
array mode, issue the Read Array command (0xFF).
Programming the Protection Register
The protection register bits are programmed using the two-cycle Protection Program command.
The 64-bit number is programmed 16 bits at a time. First, issue the Protection Program Setup
command, 0xC0. The next write to the device will latch in address and data, and program the
specified location. The allowable addresses are shown in Table 6, “Device Identification Codes” on
page 20. See Figure 18, “Protection Register Programming Flowchart” on page 57. Attempts to
address Protection Program commands outside the defined protection register address space should
not be attempted. Attempting to program to a previously locked protection register segment will
result in a Status Register error (Program Error bit SR[4] and Lock Error bit SR[1] will be set to 1).
5.5.3
Locking the Protection Register
The user-programmable segment of the protection register is lockable by programming bit 1 of the
PR-LOCK location to 0. See Figure 6, “Protection Register Mapping” on page 30. Bit 0 of this
location is programmed to 0 at the Intel factory to protect the unique device number. This bit is set
using the Protection Program command to program 0xFFFD to the PR-LOCK location. After these
bits have been programmed, no further changes can be made to the values stored in the protection
register. Protection Program commands to a locked section will result in a Status Register error
(Program Error bit SR[4] and Lock Error bit SR[1] will be set to 1). Protection register lockout
state is not reversible.
Figure 6. Protection Register Mapping
0x88
64-bit Segment
(User-Programmable)
0x85
0x84
128-Bit Protection Register 0
64-bit Segment
(Intel Factory-Programmed)
0x81
0x80
PR Lock Register 0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
5.6
VPP Program and Erase Voltages
The C3 device provides in-system programming and erase in the 1.65 V–3.6 V range. For fast
production programming, 12 V programming can be used. Refer to Figure 7, “Example Power
Supply Configurations” on page 31.
30
Datasheet
INTEL [ INTEL ]
