欢迎访问ic37.com |
会员登录 免费注册
发布采购

TE28F160C3BA90 参数 Datasheet PDF下载

TE28F160C3BA90图片预览
型号: TE28F160C3BA90
PDF下载: 下载PDF文件 查看货源
内容描述: 高级+引导块闪存( C3 ) [Advanced+ Boot Block Flash Memory (C3)]
分类和应用: 闪存
文件页数/大小: 68 页 / 1132 K
品牌: INTEL [ INTEL ]
 浏览型号TE28F160C3BA90的Datasheet PDF文件第25页浏览型号TE28F160C3BA90的Datasheet PDF文件第26页浏览型号TE28F160C3BA90的Datasheet PDF文件第27页浏览型号TE28F160C3BA90的Datasheet PDF文件第28页浏览型号TE28F160C3BA90的Datasheet PDF文件第30页浏览型号TE28F160C3BA90的Datasheet PDF文件第31页浏览型号TE28F160C3BA90的Datasheet PDF文件第32页浏览型号TE28F160C3BA90的Datasheet PDF文件第33页  
£
Intel Advanced+ Boot Block Flash Memory (C3)  
5.3  
Locking Operations during Erase Suspend  
Changes to block-lock status can be performed during an erase-suspend by using the standard  
locking command sequences to Unlock, Lock, or Lock Down a block. This is useful in the case  
when another block needs to be updated while an Erase operation is in progress.  
To change block locking during an Erase operation, first issue the Erase Suspend command (0xB0),  
then check the status register until it indicates that the Erase operation has been suspended. Next,  
write the preferred Lock command sequence to a block and the Lock status will be changed. After  
completing any preferred Lock, Read, or Program operations, resume the Erase operation with the  
Erase Resume command (0xD0).  
If a block is Locked or Locked Down during a Suspended Erase of the same block, the locking  
status bits will be changed immediately. But when the Erase is resumed, the Erase operation will  
complete.  
Locking operations cannot be performed during a Program Suspend. Refer to Appendix A, “Write  
State Machine States” on page 50 for detailed information on which commands are valid during  
Erase Suspend.  
5.4  
Status Register Error Checking  
Using nested-locking or program-command sequences during Erase Suspend can introduce  
ambiguity into status register results.  
Since locking changes are performed using a two-cycle command sequence, e.g., 0x60 followed by  
0x01 to lock a block, following the Block Lock, Block Unlock, or Block Lock-Down Setup  
command (0x60) with an invalid command will produce a Lock-Command error (SR[4] and SR[5]  
will be set to 1) in the Status Register. If a Lock-Command error occurs during an Erase Suspend,  
SR[4] and SR[5] will be set to 1 and will remain at 1 after the Erase is resumed. When Erase is  
complete, any possible error during the Erase cannot be detected via the status register because of  
the previous Lock-Command error.  
A similar situation happens if an error occurs during a Program-Operation error nested within an  
Erase Suspend.  
5.5  
128-Bit Protection Register  
The C3 device architecture includes a 128-bit protection register than can be used to increase the  
security of a system design. For example, the number contained in the protection register can be  
used to “match” the flash component with other system components, such as the CPU or ASIC,  
preventing device substitution. The Intel application note, AP-657 Designing with the Advanced+  
Boot Block Flash Memory Architecture, contains additional application information.  
The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is  
programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other  
segment is left blank for customer designs to program, as preferred. Once the customer segment is  
programmed, it can be locked to prevent further programming.  
Datasheet  
29