PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Figure 25. PC Card Read/Write Timing When System Is 8-Bit (SBHE Tied High)
-REG,
A[25:0]
t
t
3
1
t
2
-OE, -WE
-IOWR, -IORD,
-CE1
D[7:0]
Odd/even Data
Write Cycle
t
t
5
4
D[7:0]
Odd/Even Data
Read Cycle
D[15:8]
Read or
XX
Write Cycle
Table 34. Normal Byte Read/Write Timing
Symbol
Parameter
Address setup to Command active1
MIN
MAX
Units
ns
t
t
t
(S × Tcp) – 10
(C × Tcp) – 10
(R × Tcp) – 10
1
2
3
Command pulse width2
ns
ns
Address hold from Command inactive3
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (N
page 109.
× N + 1), see “PC Card Bus Timing Calculations” on
pres
val
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (N × N + 1), see page 109.
pres
val
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (N × N + 1), see page 109.
pres
val
114
Datasheet
INTEL [ INTEL ]
