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SPD6722QCCE 参数 Datasheet PDF下载

SPD6722QCCE图片预览
型号: SPD6722QCCE
PDF下载: 下载PDF文件 查看货源
内容描述: ISA到PC卡( PCMCIA )控制器 [ISA-to-PC-Card (PCMCIA) Controllers]
分类和应用: 总线控制器微控制器和处理器PC
文件页数/大小: 138 页 / 837 K
品牌: INTEL [ INTEL ]
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ISA-to-PC-Card (PCMCIA) Controllers PD6710/22  
Figure 26. Normal Byte Read/Write Timing  
-REG,  
A[25:0]  
t3  
t1  
t2  
IOWR, -IORD,  
-OE, -WE  
-CE1  
-CE2  
D[7:0]  
Write Cycle  
Odd/Even Data  
D[7:0]  
Odd/Even Data  
Read Cycle  
D[15:8]  
Read or  
XX  
Write Cycle  
NOTE: Figure 26 applies to all other byte accesses, including odd I/O cycles where -IOIS16 is low.  
Table 35. 16-Bit System to 8-Bit I/O Card: Odd Byte Timing  
Symbol  
Parameter  
MIN  
MAX  
Units  
t
Address change to -IOIS16 inactive4  
-IOIS16 inactive to -CE2 inactive  
-IOIS16 inactive to -CE1 active  
Address setup to Command active1  
Command pulse width2  
(3Tcp) + 10  
ns  
ns  
ns  
ns  
ns  
ns  
1
t
t
t
t
t
20  
20  
2
3
4
5
6
(S × Tcp) 10  
(C × Tcp) 10  
(R × Tcp) 10  
Address hold from Command inactive3  
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set  
0 default value of 01h, the setup time would be 70 ns. S = (N  
page 109.  
× N + 1), see PC Card Bus Timing Calculationson  
pres  
val  
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the  
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (N × N + 1), see page 109.  
pres  
val  
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the  
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (N × N + 1), see page 109.  
pres  
val  
4. -IOIS16 level from card should be valid before -IOWR/-IORD goes active. For a typical setup time of 70 ns, a PC Card  
meeting the PCMCIA specification for -IOIS16 from A[25:0] change will meet this condition.  
Datasheet  
115