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SPD6722QCCE 参数 Datasheet PDF下载

SPD6722QCCE图片预览
型号: SPD6722QCCE
PDF下载: 下载PDF文件 查看货源
内容描述: ISA到PC卡( PCMCIA )控制器 [ISA-to-PC-Card (PCMCIA) Controllers]
分类和应用: 总线控制器微控制器和处理器PC
文件页数/大小: 138 页 / 837 K
品牌: INTEL [ INTEL ]
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PD6710/22 ISA-to-PC-Card (PCMCIA) Controllers  
Npres and Nval are the specific selected prescaler and multiplier value from the timer sets Setup,  
Command, and Recovery Timing registers (see Timing Registerson page 84 for a description of  
these registers).  
From this, a PC Card cycles Setup, Command, and Recovery time for the selected timer set are  
calculated as follows:  
Setup time = (S × Tcp) ± 10 ns  
Command time = (C × Tcp) ± 10 ns  
Recovery time = (R × Tcp) ± 10 ns  
When the internal synthesizer is used, the calculation of the internal clock period Tcp is:  
Tcp = TCLKP × 4/7  
where TCLKP is the period of the clock supplied to the CLK input pin. An input frequency of  
14.318 MHz at the CLK input pin results in an internal clock period of Tcp = 40 ns.  
When the internal synthesizer is bypassed, Tcp = TCLKP. An input frequency of 25 MHz in this  
circumstance would also result in an internal clock period of Tcp = 40 ns.  
The timing diagrams that follow were derived for a PD67XX using the internal synthesizer and a  
14.318-MHz CLK pin input. The internal clock frequency of the PD67XX is 7/4 of this incoming  
signal (Tcp = 40 ns). The examples are for the default values of the Timing registers for Timer Set  
0, as follows:  
Timing Register Name  
(Timer Set 0)  
Value  
(Default)  
Index  
Resultant N  
Resultant N  
pres  
val  
Setup Timing 0  
3Ah  
3Bh  
3Ch  
01h  
06h  
03h  
1
1
1
1
6
3
Command Timing 0  
Recovery Timing 0  
Thus the minimum times for the default values are as follows:  
Default minimum Setup time = (S × Tcp) 10 ns = {2 × 40 ns} 10 ns = 70 ns  
Default minimum Command time = (C × Tcp) 10 ns = {7 × 40 ns} 10 ns = 270 ns  
Default minimum Recovery time = (R × Tcp) 10 ns = {4 × 40 ns} 10 ns = 150 ns  
110  
Datasheet  
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