ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
16.4.5.1
PC Card Socket Timing
Table 31. Memory Read/Write Timing (Word Access)
Symbol
Parameter
MIN
MAX
Units
-CE[2:1], -REG, Address, and Write Data setup to Command
active1
t
(S × Tcp) – 10
ns
1
t
t
t
t
t
t
t
Command pulse width2
(C × Tcp) – 10
(R × Tcp) – 10
ns
ns
ns
ns
ns
ns
ns
2
3
4
5
6
7
8
Address hold and Write Data valid from Command inactive3
-WAIT active from Command active4
Command hold from -WAIT inactive
Data valid from -WAIT inactive
(C – 2)Tcp – 10
(2 Tcp) + 10
Tcp + 10
Data setup before -OE inactive
(2 Tcp) + 10
0
Data hold after -OE inactive
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (N
page 109.
× N + 1), see “PC Card Bus Timing Calculations” on
pres
val
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (N × N + 1), see page 109.
pres
val
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (N × N + 1), see page 109.
pres
val
4. For typical active timing programmed at 280 ns, maximum -WAIT timing is 190 ns after Command active.
Figure 23. Memory Read/Write Timing
-REG, -CE[2:1],
A[25:0]
t1
t3
t2
-OE, -WE
-WAIT
t5
t4
D[15:0]
Write Cycle
t6
t8
t7
D[15:0]
Read Cycle
Datasheet
111
INTEL [ INTEL ]
