ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 36. DMA Read Cycle Timing (PD6722 only) (Sheet 2 of 2)
Symbol
Parameter
MIN
MAX
Units
t
t
t
System TC (-VPP_VALID high) to -IOWR
-IOWR to begin of card TC (-WE)4
−40
25
ns
ns
ns
7
8
9
50
50
End of card TC (-WE) to -IOWR inactive4
25
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (N
page 109.
× N + 1), see “PC Card Bus Timing Calculations” on
pres
val
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (N × N + 1), see page 109.
pres
val
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (N
4. Based on an internal clock period of 40 ns (25 MHz).
× N + 1), see page 109.
pres
val
Figure 28. DMA Read Cycle Timing
IRQ10
(DRQ)
IRQ9
(DACK*)
t
1
-IORD, -OE
(high)
-REG
(DACK* to card)
-CE[2:1]
t
t
2
4
t
3
-IOWR
-WAIT
t
t
6
5
DMA DATA[15:0]
to card
t
7
-VPP_VALID
(TC from system)
t
t
9
8
-WE
(TC to card)
Datasheet
117
INTEL [ INTEL ]
