PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Figure 27. 16-Bit System to 8-Bit I/O Card: Odd Byte Timing
-REG,
A[25:0]
t
1
-IOIS16
-CE2
t
t
2
3
-CE1
t
t
4
6
t
5
-IOWR, -IORD
D[7:0]
Write Cycle
Odd Data
D[7:0]
Read Cycle
Odd Data
D[15:8]
Read or
Write Cycle
XX
Table 36. DMA Read Cycle Timing (PD6722 only) (Sheet 1 of 2)
Symbol
Parameter
MIN
MAX
Units
t
t
DRQ (IRQ10) and DACK* (IRQ9) active to DMA cycle begin
40
ns
1
2
-CE[2:1], -REG, -IORD, -OE, and Write Data setup to -IOWR
active1
(S × Tcp) – 10
ns
t
t
t
t
Command: -IOWR pulse width2
(C × Tcp) – 10
(R × Tcp) – 10
ns
ns
ns
ns
3
4
5
6
Recovery: -IOWR inactive to end of cycle3
-WAIT active from -IOWR active
-WAIT inactive to -IOWR inactive
(C – 2)Tcp – 10
2 Tcp
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (N
page 109.
× N + 1), see “PC Card Bus Timing Calculations” on
pres
val
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (N × N + 1), see page 109.
pres
val
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (N
4. Based on an internal clock period of 40 ns (25 MHz).
× N + 1), see page 109.
pres
val
116
Datasheet
INTEL [ INTEL ]
